@misc{cit:bio_thesis,
  title = {FPGA acceleration of sequence analysis tools in bioinformatics},
  author = {Mahram,, Atabak},
  year = {2013},
  URL = {https://open.bu.edu/handle/2144/11126},
  publisher = {OpenBU}
}

@inproceedings{cit:genet_alg,
  title={Implementation of Genetic Algorithms in FPGA-based Reconfigurable Computing Systems},
  author={Nahid Alam},
  year={2009},
  URL={https://tigerprints.clemson.edu/all_theses/618/?utm_source=tigerprints.clemson.edu%2Fall_theses%2F618&utm_medium=PDF&utm_campaign=PDFCoverPages}
}

@INPROCEEDINGS{cit:bio_paper,
author={G. Chrysos and E. Sotiriades and C. Rousopoulos and A. Dollas and A. Papadopoulos and I. Kirmitzoglou and V. Promponas and T. Theocharides and G. Petihakis and J. Lagnel and P. Vavylis and G. Kotoulas},
booktitle={2012 IEEE 12th International Conference on Bioinformatics Bioengineering (BIBE)},
title={Opportunities from the use of FPGAs as platforms for bioinformatics algorithms},
year={2012},
volume={},
number={},
pages={559-565},
keywords={RNA;bioinformatics;evolution (biological);field programmable gate arrays;genetics;proteins;trees (mathematics);FPGA computing;FPGA technologies;Glimmer HMM;MAFFT;RAxML;RNA;T-Coffee;bioinformatics algorithm execution;gene prediction;high-end FPGA-based systems;multiple sequence alignment;phylogenetic tree computation;protein secondary structure prediction;sequence comparison;Algorithm design and analysis;Bioinformatics;Computer architecture;Field programmable gate arrays;Prediction algorithms;Software;Software algorithms;Bioinformatics algorithms;FPGA based systems;high performance},
doi={10.1109/BIBE.2012.6399733},
ISSN={},
month={Nov},}

@inproceedings{cit:why_faster,
 author = {Guo, Zhi and Najjar, Walid and Vahid, Frank and Vissers, Kees},
 title = {A Quantitative Analysis of the Speedup Factors of FPGAs over Processors},
 booktitle = {Proceedings of the 2004 ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays},
 series = {FPGA '04},
 year = {2004},
 isbn = {1-58113-829-6},
 location = {Monterey, California, USA},
 pages = {162--170},
 numpages = {9},
 url = {http://doi.acm.org/10.1145/968280.968304},
 doi = {10.1145/968280.968304},
 acmid = {968304},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {FPGA, VHDL, analysis, performance, reconfigurable computing},
} 

@INPROCEEDINGS{cit:compare_GPU,
author={S. Che and J. Li and J. W. Sheaffer and K. Skadron and J. Lach},
booktitle={2008 Symposium on Application Specific Processors},
title={Accelerating Compute-Intensive Applications with GPUs and FPGAs},
year={2008},
volume={},
number={},
pages={101-107},
keywords={Gaussian processes;coprocessors;cryptography;field programmable gate arrays;middleware;multiprocessing systems;FPGA;GPU;Gaussian elimination;Needleman-Wunsch;accelerator platform mapping;application-to-accelerator mapping;architectural design;code complexity;compute-intensive applications;data encryption standard;massive parallel execution resources;middleware support;multicore CPU system;programming style;Acceleration;Bandwidth;Computer applications;Costs;Cryptography;Field programmable gate arrays;Hardware;Middleware;Multicore processing;Process design},
doi={10.1109/SASP.2008.4570793},
ISSN={},
month={June},}

@book{cit:circuit_book,
 author = {Vollmer, Heribert},
 title = {Introduction to Circuit Complexity: A Uniform Approach},
 year = {1999},
 isbn = {3540643109},
 publisher = {Springer-Verlag},
 address = {Berlin, Heidelberg},
} 

@article{cit:dem_survey,
	author={Demaine, Erik},
	title={Cache-Oblivious Algorithms and Data Structures},
	journal={EEF Summer School on Massive Data Sets},
	year={2002}
}

@article{cit:book_low_bnd,
 author = {Vitter, Jeffrey Scott},
 title = {Algorithms and Data Structures for External Memory},
 journal = {Found. Trends Theor. Comput. Sci.},
 issue_date = {January 2008},
 volume = {2},
 number = {4},
 month = jan,
 year = {2008},
 issn = {1551-305X},
 pages = {54--63},
 numpages = {170},
 url = {http://dx.doi.org/10.1561/0400000014},
 doi = {10.1561/0400000014},
 acmid = {1391118},
 publisher = {Now Publishers Inc.},
 address = {Hanover, MA, USA},
} 


@InProceedings{cit:word_ram,
author="Hagerup, Torben",
editor="Morvan, Michel
and Meinel, Christoph
and Krob, Daniel",
title="Sorting and searching on the word RAM",
booktitle="STACS 98",
year="1998",
publisher="Springer Berlin Heidelberg",
address="Berlin, Heidelberg",
pages="366--398",
abstract="A word RAM is a unit-cost random-access machine with a word length of w bits, for some w, and with an instruction repertoire similar to that found in present-day computers. The simple lower bounds for the problems of sorting and searching valid in the comparison-based model do not hold for the word RAM, so that the well-known algorithms for these tasks are not optimal for the word RAM. This paper gives an overview of faster algorithms known for sorting and searching on the word RAM, many of which were developed within the last few years.",
isbn="978-3-540-69705-3"
}

@inproceedings{cit:bitonic,
 author = {Batcher, K. E.},
 title = {Sorting Networks and Their Applications},
 booktitle = {Proceedings of the April 30--May 2, 1968, Spring Joint Computer Conference},
 series = {AFIPS '68 (Spring)},
 year = {1968},
 location = {Atlantic City, New Jersey},
 pages = {307--314},
 numpages = {8},
 url = {http://doi.acm.org/10.1145/1468075.1468121},
 doi = {10.1145/1468075.1468121},
 acmid = {1468121},
 publisher = {ACM},
 address = {New York, NY, USA},
} 

@misc{cit:uses_FPGA,
  abstract     = {Since their introduction, FPGAs can be seen in more and more different fields of applications. The key advantage is the combination of software-like flexibility with the performance otherwise common to hardware. Nevertheless, every application field introduces special requirements to the used computational architecture. This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs.},
  author       = {Romoth, Johannes and Porrmann, Mario and Rückert, Ulrich},
  title        = {{Survey of FPGA applications in the period 2000 – 2015 (Technical Report)}},
  doi          = {10.13140/RG.2.2.16364.56960},
  year         = {2017},
}

@inproceedings{cit:karatsuba,
author={A. Karatsuba and Yu. Ofman},
title={Multiplication of many-digital numbers by automatic computers},
booktitle={Dokl. Akad. Nauk SSSR},
year={1962},
volume={145},
issue={2},
pages={293--294},
url={http://mi.mathnet.ru/dan26729},
}

@article{cit:strassen,
 author = {Strassen, Volker},
 title = {Gaussian Elimination is Not Optimal},
 journal = {Numer. Math.},
 issue_date = {August    1969},
 volume = {13},
 number = {4},
 month = aug,
 year = {1969},
 issn = {0029-599X},
 pages = {354--356},
 numpages = {3},
 url = {http://dx.doi.org/10.1007/BF02165411},
 doi = {10.1007/BF02165411},
 acmid = {2722798},
 publisher = {Springer-Verlag New York, Inc.},
 address = {Secaucus, NJ, USA},
} 

@incollection{cit:exp_survey,
 author = {Woeginger, Gerhard J.},
 chapter = {Exact Algorithms for NP-hard Problems: A Survey},
 title = {Combinatorial Optimization - Eureka, You Shrink!},
 editor = {J\"{u}nger, Michael and Reinelt, Gerhard and Rinaldi, Giovanni},
 year = {2003},
 isbn = {3-540-00580-3},
 pages = {185--207},
 numpages = {23},
 url = {http://dl.acm.org/citation.cfm?id=885909.885927},
 acmid = {885927},
 publisher = {Springer-Verlag New York, Inc.},
 address = {New York, NY, USA},
} 

@article{cit:alg_dom_set,
title = "Exact algorithms for dominating set",
journal = "Discrete Applied Mathematics",
volume = "159",
number = "17",
pages = "2147 - 2164",
year = "2011",
issn = "0166-218X",
doi = "https://doi.org/10.1016/j.dam.2011.07.001",
url = "http://www.sciencedirect.com/science/article/pii/S0166218X11002393",
author = "Johan M.M. van Rooij and Hans L. Bodlaender",
keywords = "Exact algorithms, Exponential time algorithms, Branch and reduce, Measure and conquer, Dominating set, Computer aided algorithm design"
}

@inproceedings{cit:opt_sort_netw,
 author = {Ajtai, M. and Koml\'{o}s, J. and Szemer{\'e}di, E.},
 title = {An 0(N Log N) Sorting Network},
 booktitle = {Proceedings of the Fifteenth Annual ACM Symposium on Theory of Computing},
 series = {STOC '83},
 year = {1983},
 isbn = {0-89791-099-0},
 pages = {1--9},
 numpages = {9},
 url = {http://doi.acm.org/10.1145/800061.808726},
 doi = {10.1145/800061.808726},
 acmid = {808726},
 publisher = {ACM},
 address = {New York, NY, USA},
} 

@article{cit:model_GPU,
title = "A memory access model for highly-threaded many-core architectures",
journal = "Future Generation Computer Systems",
volume = "30",
pages = "202 - 215",
year = "2014",
note = "Special Issue on Extreme Scale Parallel Architectures and Systems, Cryptography in Cloud Computing and Recent Advances in Parallel and Distributed Systems, ICPADS 2012 Selected Papers",
issn = "0167-739X",
doi = "https://doi.org/10.1016/j.future.2013.06.020",
url = "http://www.sciencedirect.com/science/article/pii/S0167739X13001349",
author = "Lin Ma and Kunal Agrawal and Roger D. Chamberlain",
keywords = "PRAM, TMM, All Pairs Shortest Paths (APSP), Highly-threaded many-core, Memory access model"
}


@Inbook{cit:GPU_compare_sort,
author="Grozea, Cristian
and Bankovic, Zorana
and Laskov, Pavel",
editor="Keller, Rainer
and Kramer, David
and Weiss, Jan-Philipp",
title="FPGA vs. Multi-core CPUs vs. GPUs: Hands-On Experience with a Sorting Application",
bookTitle="Facing the Multicore-Challenge: Aspects of New Paradigms and Technologies in Parallel Computing",
year="2010",
publisher="Springer Berlin Heidelberg",
address="Berlin, Heidelberg",
pages="105--117",
abstract="Currently there are several interesting alternatives for low-cost high-performance computing. We report here our experiences with an N-gram extraction and sorting problem, originated in the design of a real-time network intrusion detection system. We have considered FPGAs, multi-core CPUs in symmetric multi-CPU machines and GPUs and have created implementations for each of these platforms. After carefully comparing the advantages and disadvantages of each we have decided to go forward with the implementation written for multi-core CPUs. Arguments for and against each platform are presented -- corresponding to our hands-on experience -- that we intend to be useful in helping with the selection of the hardware acceleration solutions for new projects.",
isbn="978-3-642-16233-6",
doi="10.1007/978-3-642-16233-6_12",
url="https://doi.org/10.1007/978-3-642-16233-6_12"
}


@InProceedings{cit:FPGA_AES,
author="Chodowiec, Pawe{\l}
and Gaj, Kris",
editor="Walter, Colin D.
and Ko{\c{c}}, {\c{C}}etin K.
and Paar, Christof",
title="Very Compact FPGA Implementation of the AES Algorithm",
booktitle="Cryptographic Hardware and Embedded Systems - CHES 2003",
year="2003",
publisher="Springer Berlin Heidelberg",
address="Berlin, Heidelberg",
pages="319--333",
abstract="In this paper a compact FPGA architecture for the AES algorithm with 128-bitkey targeted for low-costembedded applications is presented. Encryption, decryption and key schedule are all implemented using small resources of only 222 Slices and 3 Block RAMs. This implementation easily fits in a low-costXilinx Spartan II XC2S30 FPGA. This implementation can encrypt and decrypt data streams of 150 Mbps, which satisfies the needs of most embedded applications, including wireless communication. Specific features of Spartan II FPGAs enabling compact logic implementation are explored, and a new way of implementing MixColumnsand InvMixColumnstransformations using shared logic resources is presented.",
isbn="978-3-540-45238-6"
}

@INPROCEEDINGS{cit:FPGA_k-means,
author={H. M. Hussain and K. Benkrid and H. Seker and A. T. Erdogan},
booktitle={2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)},
title={FPGA implementation of K-means algorithm for bioinformatics application: An accelerated approach to clustering Microarray data},
year={2011},
volume={},
number={},
pages={248-255},
keywords={bioinformatics;data mining;field programmable gate arrays;pattern clustering;FPGA implementation;K-means algorithm;K-means clustering;Microarray data;Xilinx Virtex4 XC4VLX25 FPGA;Yeast Microarray data;accelerated approach;bioinformatics application;biological problems complexity;clustering Microarray data;data mining technique;field programmable gate arrays;genome databases;genome experiments;parallel hardware design;Bioinformatics;Clocks;Clustering algorithms;Euclidean distance;Field programmable gate arrays;Hardware;Random access memory},
doi={10.1109/AHS.2011.5963944},
ISSN={},
month={June},}

@INPROCEEDINGS{cit:FPGA_matrix_inv,
author={M. Karkooti and J. R. Cavallaro and C. Dick},
booktitle={Conference Record of the Thirty-Ninth Asilomar Conference onSignals, Systems and Computers, 2005.},
title={FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm},
year={2005},
volume={},
number={},
pages={1625-1629},
keywords={Bandwidth;Computer architecture;Field programmable gate arrays;Least squares methods;MIMO;Matrix decomposition;OFDM;Receiving antennas;Signal processing algorithms;Transmitting antennas},
doi={10.1109/ACSSC.2005.1600043},
ISSN={1058-6393},
month={October},}

@article{cit:synch_circ,
 ISSN = {00029939, 10886826},
 URL = {http://www.jstor.org/stable/2041447},
 abstract = {Synchronous combinational machines are combinational machines such that the length of all paths from inputs to a logic element are the same. In this paper it is shown that any Boolean function of $n$ variables satisfying certain subfunction conditions (which are satisfied by "almost all" such functions) must have synchronous combinational complexity at least $n \log n$.},
 author = {L. H. Harper},
 journal = {Proceedings of the American Mathematical Society},
 number = {2},
 pages = {300--306},
 publisher = {American Mathematical Society},
 title = {An $n \log n$ Lower Bound on Synchronous Combinational Complexity},
 volume = {64},
 year = {1977}
}

@misc{cit:intel_combined_xeon, title={Intel Processors and FPGAs-Better Together}, url={https://itpeernetwork.intel.com/intel-processors-fpga-better-together/}, journal={IT Peer Network}, publisher={Intel}, author={Huffstetler, Jennifer}, year={2018}, month={May}}


@article{cit:rand_tree_height,
 author = {Reed, Bruce},
 title = {The Height of a Random Binary Search Tree},
 journal = {J. ACM},
 issue_date = {May 2003},
 volume = {50},
 number = {3},
 month = may,
 year = {2003},
 issn = {0004-5411},
 pages = {306--332},
 numpages = {27},
 url = {http://doi.acm.org/10.1145/765568.765571},
 doi = {10.1145/765568.765571},
 acmid = {765571},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {Binary search tree, asymptotics, height, probabilistic analysis, random tree, second moment method},
} 

@book{cit:alg_intro, title={Introduction to algorithms, 3rd edition}, publisher={The MIT Press}, author={Cormen, Thomas H. and Leiserson, Charles E.}, year={2009}} 

@misc{cit:simulate_tm,
	author={Uri Zwick and Anupam Gupta},
	year={1996},
	title={Concrete Complexity Lecture Notes, Lecture 3},
	url={www.cs.tau.ac.il/~zwick/circ-comp-new/two.ps},
}

@misc{cit:RAM_speed, title={DDR3 vs. DDR4: Raw bandwidth by the numbers}, url={https://www.techspot.com/news/62129-ddr3-vs-ddr4-raw-bandwidth-numbers.html}, journal={TechSpot}, publisher={TechSpot}, author={Sklavos, Dustin}, year={2015}, month={Sep}}