93.3625 2 clock
32.992256 the simpler risc instruct
36.979824 the second output of the risc 
50.38383 the risc instruct decod
17.180141 the operand cach stage
30.683783 the mux
63.017517 the mode regist
0.72877336 the latenc for risc instruct
57.51971 the gpr regist
2.095276 the d
47.539738 the cpu switche
71.96476 stage by a mux
17.990026 stage befor the result
75.355934 simple execut type instruct
6.271963 sequenc order
79.94399 risc mode
7.749111 m pipestag
34.231884 load/stor type instruct
61.50855 instruct from a complex instruc
35.37191 dual instruct
50.868393 comput risc
67.44437 comput cisc instruct
18.89044 compound cisc instruct
50.285435 both risc
94.62695 an operand cach stage
66.63193 an address for the operand cach
80.36431 a pipelin with a pipestag funct
67.84102 a mode bit in the mode regist
