89.98845 2 pipelin
83.23087 y processor side
19.7979 transceiv
70.38431 the same processor independ con
18.472109 the pipelin gate array
40.83472 the dual processor each access 
58.75765 the bu go from global memori on
29.497133 the bu be
31.968758 substanti resourc
61.71766 respect direct multipl access
95.52204 pipelin gate array
8.093926 own memori data regist
23.90641 overlap of backplan request
40.95194 memori select
95.85688 memori data word
71.198586 memori data
54.555798 host activ
49.889297 host
55.500328 greater depth
97.49898 global memori access
15.615285 global memori
98.70638 full buffer of read data
77.43004 full buffer
39.95391 each control processor
41.666695 dual port ram
9.896517 dual control processor
21.204088 dpr while data word
63.186733 dpr
57.701824 storag system
20.252419 redund
80.616646 the redund ram cell
39.516537 the redund map tabl
96.157845 the redund cell
23.903912 the primari ram cell in a sing
72.9599 the nest of a plural of branch p
75.81037 the event of a branch instruct
51.762917 the content of the primari ram
79.619255 tabl with chang
90.85973 tabl for use in processor
99.29664 regist renam inform in the even
67.981674 parallel with the branch instr
31.84831 branch path
75.95331 a plural of redund ram cell
52.06197 a plural of primari ram cell
64.96362 a plural of level of redund ram
36.88006 a branch stack
22.602516 dma/dsa activ
31.160934 disk array
25.6356 direct single access
43.006927 data to/from memori
9.38808 data prefetch mechan
64.099884 bu access
53.942833 an actual data
46.732418 a prefetch mechan
86.30477 storag devic
