83.74832 32-bit devic
9.406704 use of an address decod
96.29719 the dma mechan
7.5716963 the cycl on the cpu
37.242855 the address decod
71.44248 that event
3.7137547 proper interfac between a dma 
67.292595 oper in a microcomput system
18.180809 dynam bu size
82.15059 devic address for cacheabl devi
58.75841 definit cacheabl devic
33.621643 complet of the previou cycl
83.64906 complet of the dma cycl
44.343792 ani incompat
53.589386 ani devic address for non cach
11.933948 an interfac between the cpu
31.666744 a next address signal i
43.562325 a dma cycl
64.49014 a cpu local bu subsystem
21.493979 a cacheabl devic
87.748146 82385 cach control
