48.8039 the bu request
3.8876386 thi implement
69.79726 the respect bu arbit
84.80889 the next immedi clock cycl
89.560646 the next bu master
78.83358 the maximum system clock freque
47.228615 the last port driver
25.289806 the current bu master
95.36546 the critic time path
3.2872386 the bu master
20.631418 the arbitr system
27.204737 the arbitr protocol
30.57187 the arbitr process
31.986382 the arbitr latenc
26.731071 the arbitr clock cycl
35.03232 technologi
99.81795 system clock cycl while the lat
38.792065 overal system clock latenc
43.764946 each arbitr task
5.265722 bu request line in a first cloc
1.3035194 bu master
94.106384 bu content
53.525967 bu arbitr system
46.320347 bu arbit
24.52048 ani system
9.919185 ani chang
34.573517 an inact system
19.339817 an arbitr clock cycl
41.96321 a system clock cycl
41.878853 a second clock cycl
24.664026 a last port driver
9.461414 a current bu master
75.303185 a common system
38.270638 a bu request in a clock cycl
