-which make the protocol
valid/setup/hold of the processor
the indic on the privat interfac
the dual process protocol
the core frequenc
the comput resourc
the bu fraction ratio
the board
robust arbitr dp protocol
pure bu clock domain
privat interfac paramet
partial control of the bu i
intern cach line
high core frequenc
futur upgrades/product with much higher intern frequenc
flight time
differ bu fraction
comput perform
bu transfer
an effici manner
a robust dual process protocol
a pure bu clock
a dual process protocol between processor
a dual process protocol

the second output
the visual state of the comput
the second portion of the address inform
the second output of the first mean
the first output
the backup system
the fifo queue
the address inform
second portion of the address inform
second output
more destin locat in the regist file befor that destin locat
hardwar devic
further inform
destin locat in the regist file
backup than a compar softwar
backup queue
a second portion of address inform for backup storag of the regist file content
a regist file with a plural of address locat
a regist file backup system for use with a comput
a previou state if an instruct
a first portion of the address inform

2 clock
the simpler risc instruct
the second output of the risc instruct decod
the risc instruct decod
the operand cach stage
the mux
the mode regist
the latenc for risc instruct
the gpr regist
the d
the cpu switche
stage by a mux
stage befor the result
simple execut type instruct
sequenc order
risc mode
m pipestag
load/stor type instruct
instruct from a complex instruct
dual instruct
comput risc
comput cisc instruct
compound cisc instruct
both risc
an operand cach stage
an address for the operand cach stage
a pipelin with a pipestag function unit
a mode bit in the mode regist

2 pipelin
y processor side
transceiv
the same processor independ control program
the pipelin gate array
the dual processor each access independ control store ram
the bu go from global memori on read oper
the bu be
substanti resourc
respect direct multipl access
pipelin gate array
own memori data regist
overlap of backplan request
memori select
memori data word
memori data
host activ
host
greater depth
global memori access
global memori
full buffer of read data
full buffer
each control processor
dual port ram
dual control processor
dpr while data word
dpr
storag system
redund
the redund ram cell
the redund map tabl
the redund cell
the primari ram cell in a single clock cycl
the nest of a plural of branch predict
the event of a branch instruct
the content of the primari ram cell in a single clock cycl befor the processor decod
tabl with chang
tabl for use in processor
regist renam inform in the event of a branch mispredict
parallel with the branch instruct
branch path
a plural of redund ram cell
a plural of primari ram cell
a plural of level of redund ram cell
a branch stack
dma/dsa activ
disk array
direct single access
data to/from memori
data prefetch mechan
bu access
an actual data
a prefetch mechan
storag devic

track
the use of the avail data
the peripher devic command from the comput
the peripher devic command
the occurr of subsequ read data transfer command
the lbpi
paramet of the peripher devic
a high perform local bu peripher interfac
a countdown of the number of word of a data sector

a second mode
user routin
the shadow subset
the second subset
the regist system
the first subset
system routin
subset
second subset
risc microprocessor architectur
point width data in respons
point regist for sourc data
pipelin disrupt
particular integ
integ width data
instruct access
ident bank of regist set
fix locat statu flag
complex boolean comparison
boolean regist
boolean comparison instruct
boolean combin instruct
ani attempt
an integ regist
a shadow subset
a regist system for a data processor
a re typabl regist
a plural of mode
a particular boolean
a first mode

2 stage of the i-2 instruct
variabl length pipe oper
the sasm time
the processor in a first mode
the perform of the processor while the stack mode
the other mode of execut
the nth stage of the ith instruct
the non stack mode of execut
the execut of instruct in the same sequenc
stack mode
sequenc logic
order of the execut sequenc
order instruct
null instruct stage
non stack mode
execut of a particular instruct
all section of an instruct
a time equival
a stage befor processisng the next stage

2 window architectur
window transform
window neighborhood transform scheme
simple circuit compon
raster scan revers in combin
effici transform
a neighborhood transform modul

2-d discret cosin
a pre processor stage
a dct circuit

22
variou function unit
variabl width operand
thi method of depend resolut
the variabl width regist operand structur
sever partial operand field
regard for the type of data
partial bit field of a regist operand
parallel process of oper that act
parallel perform of oper
parallel perform
parallel handl
operand data of variabl bit width
independ depend
implement of regist
dispatch multipl rop
data structur
data in these field
bit width operand
a substanti improv

223
y trace draw oper
y trace be
y co ordin valu
x trace be
the two dimension surfac chart in accord
the surfac a a first matrix
the same y valu in the first matrix
the same x valu in the first matrix
the point of the second matrix
the part of an y trace fall
the first matrix into a second matrix
sequenti draw oper
sequenc from low y valu
no line
line in a two dimension surfac chart
high valu
d
an y trace be
an x trace be
an upper horizon
an imag of a three dimension surfac
an area
a second angle
a lower horizon
a first angle

24
util of the video ram memori space
these mode
the video ram
the video memori
the select color mode
the ramdac
the data in the video memori
the data from the video memori
place data
flexibl graphic interfac for multipl display mode
data into analog signal
address space
a user select color mode
a serial output port of a video ram
a ramdac
a host microprocessor
a graphic interfac modul
a graphic interfac circuit
a graphic display processor into a video memori
a display system of the type
64k
32k
32 bit wide output on the data

24-bit mode
exact mode
both 24-bit arithmet
both 24 bit
an entir instruct
a transit between mode
a multiply/accumul oper
a data alu

24-bit operand at nanosecond rate
wide dynam rang digit receiv
the wide dynam rang
sum of product
sonar applic
signal through the use of a special purpos
digit receiv processor
a wide dynam rang digit receiv for radar

256
wide structur
two level branch predict cach
the bpc
partial predict inform
number of branch instruct
narrow structur
level of branch inform
level bpc
each branch instruct
cach full predict inform
associ first level bpc
a much larger number of branch instruct
a hybrid cach structur
36

256 5-bit element per vector
use in the classif mode
the supervis of a system administr controller/cpu
the rel probabl of variou class membership
the prototyp vector
the prototyp fire
the input vector
the distanc between the input vector
the distanc between input
the classifi chip
the classifi capac
probabl paramet
parzen window
neural network classifi chip
multichip oper
high dimension input pattern vector
distanc
class membership
class fire
base
appropri train vector
an adapt distanc
addit prototyp
a programm threshold distanc
a probabilist model
64 class

256 imag
variou partial neighborhood oper
the same number of processor element
the imag signal processor
the architectur of the imag signal processor
output pixel of data
lsi
input pixel data
imag signal processor
expans of a partial oper area
a partial parallel type imag
a parallel oper
a gray level imag
6 mhz
256 tone at a video rate

time slot
virtual processor request
virtual processor
the highest prioriti array
the array of virtual processor time share a common execut unit
storag unit
secondari control
prioriti among the array
multipl execut facil
machin time
execut unit share by plural of array of virtual processor
each virtual processor
each array
a virtual processor
a single execut unit
a prioriti control
a multipl of servic request
a multipl of array of digit machin
a multipl of array
a digit machin
a candid for present
a basic digit comput

263
video imag data
the h
p frame
p
variabl m
these cell
the variabl n
the variabl m
the output of a previou calcul cell
the cell over a period of q time slot
parallel over the cell
m n
echo cancel
devic with a plural
an echo cancel
an adapt finit input respons filter
an adapt finit impuls respons filter
a systol arrang
low power video decod system with block base motion compens
b predict process
an on chip central process unit
a batteri power comput system

27
word format within ani degrad
type field
the avail address
the arithmet pipelin
sourc of operand
sourc for operand
sourc data in byte
reciproc operand
pointer pipelin
pair with counterpart oper
markov model
instruct format
full flexibl
dynam time
arithmet pipelin
comput within an arithmet pipelin
combin for each instruct format
an instruct format
address instruct format
a pointer pipelin
a destin for the result of the comput unit
pattern recognit system
address arithmet logic unit
address arithmet unit

29
the instruct on the basi
the instruct address
the addit result
that jump instruct
result by the instruct
instruct from a memori
an address of the instruct
a valu of a branch displac field
a branch target address calcul unit

2d data
vram block
system with multi pixel span
span fragment
parallel process of multipl pixel in a serial architectur
optim condit
multi pixel span fragment
architectur with select process of multi pixel span
3d graphic process

2d oper
window ownership identifi
three dimension graphic subsystem
these identifi
the window posit
the innov system
the 3d
the 2d
support for graphic user interfac
substanti 3d
rapid perform of 2d
period of 2d
dual independ context
demand
the same time that second instruct inform data
second oper cycl
method by a processor
instruct inform data
first instruct inform data
demand in a pipelin processor
address data of instruct inform data
accord with the first instruct inform data
a pipelin control mode
a first oper cycl of a seri
both 2d
a certain percentag of cycl
3d

2k pe
vax assembl code
the scalar front end processor
the pipelin in pe
the parallel vector machin model
the parallel pe
the memori hiearchi
the fundament idea behind the parallel vector machin model
the execut of a number of risc oper
the cm-2 target machin
the 2k processor
techniqu along the peac instruct
sparc
sourc program onto a cours grain hardwar
peac
own interfac
each pe
differ level of parallel
data distribut
comput cm-2 system
cm fortran
a varieti of parallel process machin
a target machin
a parallel vector machin model
a new risc like instruct
a new compil phase
a machin
a fine grain array base sourc program
a fine grain array
a cours grain hardwar
a collect of thousand of vector processor
64k simple bit serial processor

a bu structur
the unit of a modul check
the prioriti of each unit
the oper of the bu structur
the common bu structur
the bu structur
signal other modul unit
simplic
signal for error
partner
more peripher control unit
modul with access
interrupt in the event of fault
inform transfer between the unit
inform transfer
inform handl part of the system
fault free unit
fault free conductor
fault free bu conductor
error detector
erron inform onto the bu structur
each system unit
arbitr circuit
a processor unit
a fault toler comput system

an intern data memori
the intern oper
parallel data input/output port
parallel data commun with an extern devic
input/output oper
imag signal process
high throughput
dma transfer
block data input/output between the intern data memori
block data
asynchron fashion
an intric adapt process algor
an intern oper by the arithmet oper
an extern data memori
an arithmet oper
address for the intern oper
a program control
a plural of 2-port memori
a dma control

a second decod
a first decod

2n bit data
the second oper unit
the multipli add oper
store the respect n bit data from the first oper unit
regist of the regist file
parallel with the oper of the second decod
parallel in the form
decod an oper code for a multipli add oper
decod an oper code for 2 data
caus
thi valu
the processor instruct unit for use a a millicod branch condit
the processor in the system
the output of thi latch
system with a milli mode oper
quiesc request
an output of the processor
all processor in the system
a single bit of a millicod control regist
a quiescent state
a milli mode routin handle a quiesc
an operand access unit
a second oper unit
a first oper unit

2n bit word in a doubl precis mode
the amu concaten
the amu
sever arithmet oper on the operand
n bit word in the doubl precis mode
n bit word from the memori in a single cycl
n bit part
n bit operand from the memori in a single pipelin cycl
either single precis
doubl precis arithmet oper on data
doubl precis
consecut memori locat in a single cycl
arithmet oper on n bit word in a single precis mode
an arithmet manipul unit
address in respons
a single precis mode
a second pair of n bit part from the memori
a second 2n bit operand
a multi port memori
a first cycl
a doubl precis oper
a doubl precis mode
a 2n bit operand

2n time
the pipelin arithmet logic unit
a plural of pipelin arithmet logic unit

2x architectur
the nonvolatil memori design
the nonvolatil memori architectur
mhz oper
low voltag row decod
low voltag control circuitri
high voltag row decod
gate memori cell
gate memori architectur
data multiplexor
data multiplex
a plural of memori array
a nonvolatil memori architectur
a master/slav portion increas the data access rate

the way
the state of the condit code among the group
the previou condit code
the new condit code
the condit code a a result
the comparison result
millicod instruct for rang
instruct compar
a rang check instruct sequenc
a logic comparison
32-bit valu
3 if the first operand

3
the plural of ga cylind
the low pressur manifold
the high pressur manifold
the flow of ga through the high pressur manifold
ship
ga cylind
each storag cell
each control valv
a submanifold
a single control valv
a ship
a plural of ga cylind
a low pressur manifold
a high pressur manifold
a cell manifold

3 cpu
these intern test point
the third cpu
the serial scan chain string
the serial data from other cpu
the serial data from each cpu
the result from each cpu core
the multipl cpu
the die
the cpu core into a serial chain
sever cpu core
self test multi processor die with intern compar point
pariti from intern test point
pariti
the self test mean
the test vector gener
the test result in the memori
the test result
the pariti check principl
the memori at a slower rate for the highest prioriti
the clock rate of the pipelin processor
self test pipelin processor
coupl pariti
clock rate of the pipelin processor
arithmet modul
an on line test of memori modul
an off line test at the processor clock rate of both memori
a ram
a pariti encod
output mismatch
other cpu
no error
match
intern test point within each cpu core
high traffic area in the pipelin
error for each cpu
each test clock period
each cpu core
each cpu clock cycl
cach while result from other cpu
an inexpens extern tester
a third cpu
a test clock
a serial scan chain
a self test mode
a self test circuit on the die
a microprocessor die
a larg second level cach on the die

3 flip flop regist
the success stage of the calcul
the same calcul by repetit of the same control instruct
the polynomi oper in the galoi field of the invent
the output of the regist
the coeffici of the result polynomi in the galoi field
reed
polynomi oper in galoi field
input x
digit telecommun
digit data in the form of octet
bch
an oper of thi type
a third level for calcul
a so call pipelin level
a multiplex level

3-bit group
two phase intern clock
the wallac tree function
the multiplicand
the chip area
restart
partial product term
other aspect of the invent
number of adder of a convent implement
new operand
iter use of the csa array
a seri of 8-bit slice
a high speed binari multipli circuit

3-d array
thi embodi
the ieu
the gru
the graphic data oper
pixel distanc oper
graphic oper from each categori
expans
the helper
the execut perform of the non complex instruct
the complex instruct
non complex instruct execut
non complex instruct
each non complex instruct bypass the helper
complex instruct into microinstruct
complex instruct in an out of order processor
a by passabl helper
a bundle of instruct
condit store oper
align address
a second categori
a number of graphic oper in accord
a number of graphic data format
a number of graphic data edg
a number of graphic data addit
a graphic statu regist
a graphic execut unit
a graphic data align address

3-d tool posit
the target coordin for the tool
the seam
the oper corner
the digit express of the video imag of a light stripe
target for the tool
system for an optic seam tracker
symbol attribut of the graph
such match
standard seam
signal repres of a one pixel wide line
a seam

the scalar processor
vector instruct from an instruct cach
the scalar/vector processor
the perform of the scalar/vector processor
the oper of those instruct
the instruct control mechan
logic instruct
high perform scalar/vector processor
an instruct control mechan
a scalar processor
a plural of independ function unit
a multipl of pipelin
a minimum number of gap

32 bit
vector processor in parallel
the parallel dsp chip
the oper of a 24-bit scalar processor with anoth group of bit
the next structur in an array of structur
the element of the structur by the simultan oper of the vector processor
the basic program concept
the address by the number of byte in the structur
softwar stack pointer
softwar develop
single task oper system
parallel digit signal process
parallel by an instruct word
operand for use by the vector processor
most instruct word
more array of four element structur
memori util
memori address space
mb
group of bit
everi instruct word a a result of the parallel architectur
each instruct word
c compil
a single task

32 bit x86 processor
the transfer of instruct byte from the target prefetch block
the segment limit violat state
the segment limit
the prefetch unit increment a prefetch physic address pfpa
the pfla
the low order bit
the linear address
the full target linear address
the csla address
the csla
the code segment limit linear address csla
target address inform
such target prefetch block
segment limit violat for branch target
prefetch linear address
prefetch block
each prefetch address
ani instruct byte from the target prefetch block
a segment limit violat state
a segment limit violat
a prefetch address thi target address inform
a partial match
a full pfla for comparison with the csla
a cof hit in the branch unit

32 byte from an extern memori sourc
the extern bu transfer 32 byte per transact
the detail of cach organ
respons the bu interfac unit
processor bu interfac
no tight commun with the processor
little overhead i
embodi a cach memori
ani extern bu transact
an effici interfac between a cach memori
a subsequ request from the cach memori for a memori block
a particular number of byte per request
a differ number of byte per bu transact
a bu interfac unit of a processor system

32-bit devic
use of an address decod
the dma mechan
the cycl on the cpu
the address decod
that event
proper interfac between a dma mechan
oper in a microcomput system
dynam bu size
devic address for cacheabl devic
definit cacheabl devic
complet of the previou cycl
complet of the dma cycl
ani incompat
ani devic address for non cacheabl devic
an interfac between the cpu
a next address signal i
a dma cycl
a cpu local bu subsystem
a cacheabl devic
82385 cach control

a processor core
the processor core

32-bit operand data
the width of the operand buss
the result buss
the operand buss
the excess capac of the result buss
the concurr execut
suboperand
wider width
result buss
point operand data into multipl suboper
point function unit recombin the suboperand data
point function unit
point data
either integ
partit the 82-bit result for output
operand buss
integ transfer
integ function unit
integ flag
data handl dimens from the standard integ data width of 32 bit
82-bit operand data
point superscalar
plural operand buse of intermedi width
narrow width integ
point processor core for a superscalar microprocessor with a plural of operand buse
operand segment

32nd bit posit
width
the second mask
the rang boundari
the proper check of an overflow condit
sever arithmet oper
the right
the program bitwis and the origin intermedi signal with the first mask
the minimum rang boundari
the maximum rang boundari
the intermedi signal i within the rang boundari
the intermedi signal i
the first mask valu
the first mask signal i
the data signal
bitwis or
neg overflow state
posit the second mask signal
program control
lower bit
integ in case of overflow
compliment format
binari valu
an intermedi regist
a manipul
a first mask
a comput result

3d color imag
view direct
the product of 3d color imag
the fmac
the flow of data for the system
signal characterist
scheme of time
locat in the regist file
light sourc
light signal
light direct
convent technologi
control of the system
an input queue
a normal unit vector
a next cycl

3d histogram
the facial area detect unit
state of facial part
similar principl
posit of the facial area
pixel valu frequenc
mouth area
imag of facial express
facial area signal
eye area detect unit
backproject
a real time output
a facial area detect unit

the graphic control
a graphic control

low level cach
inclus state

a second mode of oper
a first mode of oper

3d pipelin
the second oper regist
the first oper regist
the command processor
the command parser
the applic
second oper regist
method for graphic data concurr
low latenc for 2d pipelin
higher prioriti
graphic resourc between 2d
graphic resourc
graphic command from the applic
graphic command from applic spawn pipelin
concurr among multipl pipelin
coher
unit for access
the state of a line
the second mode of oper
the low level cach
the l2
the high level cach snoop a request
the first mode of oper
the data in the high level cach
no data
mesi
low level inclus bit
data in the high level cach
data from the low level cach
collis between a processor request
a system request
a retri
a cach line
bltbit engin access
an arbitr scheme
a command parser
a bltbit engin

3d space
valu of the characterist along the surfac of the polygon
the slope of the main slope
the slant of the main slope of the polygon
the orthogon slope valu
the orthogon slope
the magnitud of the error valu
the magnitud of the error
the fraction compon of the x paramet overflow
the error valu in the opposit direct
the error valu
the characterist of the pixel in the scan line
polygon into a pixel grid
orthogon slope
intersect line between polygon
error valu
error in pixel characterist
characterist valu
an interpol
an increment orthogon error correct process for 3d graphic
abrupt chang in the characterist of adjac pixel
a polygon into a pixel grid
a pixel shift of the scan line

prefetch buffer
the prefetch buffer
a branch target cach
the btc

4 entri
victim
the victim of a miss
the next slower level in the memori hierarchi
the miss cach
the basic stream buffer
stream buffer
some instruct cach
small victim cach
second level cach
prefetch techniqu
prefetch cach line
multi way stream buffer
data refer stream
cycl miss penalti
compulsori cach
an improv
an extens
a small fulli associ miss cach
a mani cycl miss penalti without the miss cach
a cach miss address
miss in the cach
method with prefetch buffer
method with small fulli associ cach

45
the second operand regist
the second multipl operand
the second addit operand
the first operand regist
the first multipl operand
the first addit operand
the addit result regist
the addit result buse
second multipl
second addit operand buse
circuit of a small size
anoth input of the multipli
anoth input of the adder
an input of the multipli
an input of the adder
an addit result regist
an addit result
a vector calcul unit
a pipelin adder
a first multipl
a first addit operand
52
48

48 bit
thi frame processor
the other compon of the system
the calibr
sever function
radioact decay correct
puls height resolut
puls height analysi setting
narrow energi window
millisecond in the case of a gamma camera
individu channel in multi crystal camera
function within the shortest data accumul time of the camera
frame processor
field uniform
electrocardiogram digit
digit imag frame processor
digit array spectroscopi in real time
detector dead time
data correct
correct of all scintil data
consequ
bit slice comput technologi in an arithmet logic unit
background
the multipl candid binari imag
the imag background
the highest qualiti binari imag
the binari imag
text in the foreground
text a foreground
process paramet in a contrast base histogram evalu
multipl set
multipl candid
gray scale imag
foreground from background in imag
dirt
binari imag
a wide varieti of text font
an array mode
acquisit

486-type microprocessor
valid bit
the valid bit
the prefetch queue
the load of a prefetch queue
the except statu regist for valid except
the except processor
the appropri except
techniqu of the invent
number of except condit
invalid that instruct byte
instruct byte thi valid bit
except statu inform
each stall condit
ani instruct byte
an invalid instruct byte
an except statu regist
an except processor
a stall condit
a potenti except condit

5 mip perform
support other global memori
simimd
signific softwar flexibl
signific memori
scalabl system
quick implement
program compat
processor on a single chip
person comput applic
parallel applic
no memori access delay
new util a chip densiti increas
new softwar
new pinout
new hardwar
network topologi
memori with multipl pme
low power cmo with dram
intern port
hypercub
higher rang
global memori function
extern port
extern connect for broadcast
expand technologi
element on a single chip
dynam switch of mode
dasd
convent microprocessor mmp
common languag
bit processor with 32k
bit processor
avion comput system
asynchron simd
a vision
a single node of a fine grain parallel processor
a parallel array processor
a microprocessor acceler
a hypercub
a chip function
64

5 n
use with level 2
the variou clock signal
the sram interfac
the other compon that interfac with the sram
the oscil
sub-5 nanosecond
sram structur
level 3 cach sram memori devic
level 3 cach memori devic
level 2
depend on the same clock event
cycl steal time from multipl cycl
clock edg relationship
access time

the origin imag
these capabl
the result of the variou oper
the print data
the merg unit
the merg oper
the lossless print data
the lossi print data
the lossi
the halfton oper
the direct memori access control for further process
the color space convert
storag in system memori
qualiti
print data into lossi
print data for text
print data for imag
placement of the color space convers oper
pipelin for use in a color electrophotograph printer optim
memori usag
lossless print data stream after decompress
lossless print data
lossless compressor/decompressor
lossless compress oper
lossless compon
lossi print data
lossi
line art
high compress ratio
halfton unit
further optim the print qualiti
feedback path within the print data
each type of print data
configur of the print data
bypass path in the color space convert
applic of the print data compress oper
a print data
a multitud of permut of print data
a merg unit
a direct memori access control

serial neighborhood processor
the stage in the pipelin
the fabric of electron compon
geometr constraint
composit imag matrix
bit map represent of sever ic mask
all necessari data
adher
a pipelin of programm serial neighborhood stage

5 pixel neighborhood
the serial pipelin combin of a plural of transform neighborhood
the serial digit data
the serial data digit imag processor
serial process
serial digit data
more effici process
interconnect verif
interconnect artwork for electron compon
flaw in the origin imag artwork
each pipe element
ccd imag pickup element
a serial data imag
a programm serial imag processor
a plural of pipe element
a number of neighborhood imag enhanc techniqu
5 pixel neighborhood array

54
the video system
the variou storag plane
the simultan process
the interact simultan digit process of the imag
the imag compon
the digit imag
simultan process
separ imag storag plane
real time on a televis monitor
other interact devic
other imag data
other control circuitri
interact video product system
interact imag
imag plane on a pixel by pixel basi under interact control of a keyboard
imag inform content
imag combin circuitri
green imag compon
graphic plane
graphic control data
format of the imag plane
either system
differ imag
differ digit control mask for each pixel
data tablet
composit color imag
an rgb format
an interact film
a pixel by pixel basi
a pipelin processor configur
a displayabl result composit color imag
86
78

56 gigahertz
type mechan
the increment natur of the processor
the increment mechan
the high process rate
signal enhanc
reduct
transform processor system
parallel pipelin architectur
output paramet
other digit filter oper
microwav sample rate
microsecond for an effect sample rate
low cost capabl
integration-after-transform yield high process gain for signal-to nois ratio enhanc
integr
input mechan
increment digit convers
high data
correl
increment digit filter
an increment digit filter
a simple arrang with a low compon count for low cost
a parallel pipelin architectur in combin with increment process
a bu output structur

6 byte in length
the valu of each tag
the instruct length code
the field posit for the op code
the commenc of a compound instruct
parallel execut compound of scalar instruct
op code
more instruct from an instruct stream
length of each individu instruct
instruct length code
field locat
correct tag valu
candid
appropri tag
an actual instruct boundari
a complet sequenc of possibl instruct

matrix multipl
the comput processor
respect stage of the data pipelin
polynomi equat
output signal
oper in a logarithm number system
more data stream
mathemat oper
infinit impuls respons
finit impuls respons
domain
differ equat
configur the comput processor
an invers log convert
an input log convert
a second data pipelin
a programm accumul
a first data pipelin
a feedback log convert

64 bit by 64 bit
the matric within a vector processor
the matric
matric in a vector comput system
bit manipul of data in vector regist of a vector regist comput system
anoth 64 by 64 matrix
a vector matrix multipl function unit
a result vector regist
a matrix result
a bit level of data
a 64 bit by 64 bit matrix

64-bit data block on each cycl
variou data width
unit of the cpu
instruct of variabl length
flexibl in instruct execut time
macroinstruct
a wide bandwidth

64-bit operand execut pipelin
upper 32 address bit
the upper 32 address bit for the target
the upper 32 address bit
the super page address
the sequenti instruct stream
the branch pipelin stall until all other branch instruct
the branch pipelin
super page regist
sequenti sub address regist in the branch pipelin share
sequenti address for condit branche
sequenti address adder
mi predict recoveri
instruct with the same upper 32 address bit
extenst of 32-bit architectur
bit 32 in the 32-bit target
an instruct refer an address in a differ 4
all 32-bit target
a super page cross
a 4
a 32-bit branch pipelin
64-bit target

dct
yuv represent
yuv convers
thi system
thi represent
the video signal i
the revers of compress step
the invers discret cosin
the form
the dct circuit
the dct
the chromin compon
system for compress
rgb
quantiz
matric of pixel in the rgb signal format
matric in a zig zag manner
huffman code
decompress of video data
decompress of the signal i
decompress counterpart
dct coeffici
amplitud below a set of preset threshold
a step
a quantiz step
a discret cosin
a digit video compress system

7
video signal process
variou type of logic comput
plural of parallel process unit
pipelin memori 5
pipelin memori
invers discret cosin transform
inner product comput
imag data differenti process
imag data addit
imag compens
encoding/expans
data selector
comput of absolut valu of differ
comparison of magnitud
block of imag data of a size
an intern pipelin memori in the aforesaid process unit
adapt video signal process

the program bitwis and the intermedi result with the first mask
the first mask
the data signal i in an overflow state
program control with the program
an upper threshold
an intermedi result
a second mask
a manipul of data signal
a lower threshold
8-bit integ in case of overflow
8-bit binari valu
8 lower bit in the off posit
8 lower bit in an off posit

8 bit integ
the intermedi result signal i insid the rang
the intermedi result signal i in a posit overflow state
the data signal i in a neg overflow state
a neg overflow state

8 dct matric
typic data set
tradit spatial domain method for invers motion compens
tradit spatial domain method
the standard syntax
the spatial domain represent
the spatial domain block in the current pictur
the reduct in comput complex
spatial domain
multipoint video
motion
invers motion compens
fast dct domain
down imag
domain without explicit decompress
domain result in comput saving
domain represent for video
domain represent
comput complex
a varieti of applic
a sequenc of dct domain block

86-compat processor
the comput memori
the align
specif locat in a comput memori
sequenti align fault
privileg level
method for memori address align doubl fault
gener of the align check except
error handl circuit
an applic task
an align fault
an align detect circuit
an align check except in respons
align with respect
a third sequenti align fault
a sequenti align fault
a lowest privileg level
a doubl fault except in respons

use of request byte by function unit
the processor critic path
the align function
system for data align
specif byte request
shorten the critic path in the memori access stage of the processor
prior art data align network
obviat the typic memori processor mismatch delay
byte by the function unit
a regist devic within a cpu
a function unit within a comput system effect the return of a word

a 2
the upper n bit of the doubl precis data
the doubl precis multipl
single precis data
doubl precis multipli
doubl precis data
complement single precis multipli
bit of the doubl precis data
bit doubl precis data
anoth single precis data
a doubl precis multiply

a front end processor
the system architectur
the macrocod instruct sequenc
symbol languag data
symbol languag
stack cach window
procedur call
parallel data type
page hash tabl cach
other peripher
microcod support
intercommun
pointer control a close connect of the macrocod
garbag collect
error correct circuitri
a synergist combin of the lbu
a symbol languag data
a sequenc unit
a page hash
a novel bu network
a data path unit
a common lbu
a uniqu insruct
a close connect of the macrocod
pointer control

a 2-dimension array of control point
weight
valu from pixel in the neighborhood of a particular pixel
the weight of the pixel
the valu of the pixel
the target for possibl chang
the pixel in the neighborhood of a target pixel
pixel in the neighborhood
line and/or dot
each line
chang in the target pixel
boolean imag data
account by a summat of the result of the multipl
a weight by use of a weight
a medial axi for each imag
a centroid line of an imag
the rest of the graphic system
the patche
the paramet for the ration bezier
the coordin of the corner point
system for graphic
surfac patche for both wirefram
parallel surfac
parallel process system
normal at the vertic of the small patche
model in a raster graphic display
a transform processor

a 2-port memori
write in i
two port memori
three dimension comput graphic
the serial port of the 2-port memori
the random port of the 2-port memori
the depth inform read
the depth inform
the 2-port memori
depth inform
a serial port
a result of the pipelin
a random port

scalar oper
scalar operand
scalar instruct
more data processor
both vector operand
both vector oper
both vector instruct
a single microsequenc
a memori circuit

a 25 mhz
the vpu
the highest possibl throughput per volum
mhz vector
i/o of vector data
high speed process of larg vector
control portion
control function scalar oper
complex arithmet vector processor

a 3 time booth recod multipl
the final result from the booth recod multipli
the final multipl result from a lower order product
the entir product
each bit of the multipli operand a 3 time booth recod
a fast sign
a contribut
a booth recod multipli array

a 32 bit
the quantiz
the factor
the addit section
rapid set of addit
imag compress
arithmet simplic
a set of multipl
a final multipl

a 32-bit bu
the sequenc of compar
the error correct circuit
parallel synchron header correct machin for atm
minimum process delay at an atm node
error statu flag for an atm cell processor
atm cell with multipl error
an error correct circuit for an atm header of an atm cell
a sequenc of synchron compar circuit
a correct mask

a 3d imag
three dimension imag
the spatial coordin valu of the 3d imag
the rotat plane
the pixel spatial coordin valu
the pixel coordin
the imag through three dimension space
the 3d imag
rotat of the 3d imag about the axe of three dimension space
project of the imag
project
pixel spatial coordin valu
orient a 3d imag
coplanar with the rotat plane
angular orient in a three dimension space
angle about the perpendicular axi
an axi
an arbitrari angle
a three dimension spatial coordin valu
a rotat plane of the three dimension space
a grey scale valu

a 4 byte longword
the natur boundari
the execut effici of system with a single instruct length
the bit field of the instruct word
the appropri function unit
term of the smallest machin
system for concurr dispatch of instruct
simultan oper of all avail function unit
power of 2 in length
method for concurr dispatch of instruct word
maximum oper effici
length of the instruct word
instruct compon
effici of variabl length instruct
an execut cycl
an 8 byte quadword
a compon of an instruct word

a 64 bit width data oper
the low order 32 bit arithmet devic
the high order 32 bit arithmet devic
the arithmet devic
the 64 bit with data oper a an arithmet devic
parallel process by an operand effect address calcul unit
oper control
anoth arithmet devic in the instruct execut unit
an operand effect address
an arithmet devic in the operand effect address unit
a way that a high order 32 bit oper
a plural of arithmet devic
a low order 32 bit oper

the oper result
an oper result

a a/d convert into a digit signal
the third memori
the power of a spectrum
the oper result of the last oper stage
the acoust emiss
second input memori of the next oper stage
second input memori
oper a a whole
micro fractur detector
an acoust emiss
a third memori
a rotat vector
a pickup
a cascad connect of a plural of oper stage

a accumul oper processor
the potenti util of thi architectur design
the number of pixel in the imag
the natur decomposit of algebra function
the merit of thi architectur design
the logic comput architectur
the logic architectur
the effect of thi particular decomposit
the control buffer
power fundament formul in the algebra
point wise oper
matrix product
logic oper of the imag algebra
high perform architectur for imag
concept
ani number of physic form
an imag algebra
all digit implement
all common imag to imag transform
a wide rang of applic
a substanti increas in throughput
a spatial configur processor
a point wise oper processor
a hybrid electro optic implement
a function of the number of element in the templat

a arbit
variou interfac circuit
use in an imag manag system
thi transfer
thi rip
thi point
thi pipe line oper
these compon
the throughput of the rip
the sourc compon
the destin compon
the avail
task while the destin compon
respect task
respect imag
raster imag processor
other of these imag
other imag
engin at a high rate
destin compon
a scaler
a respect imag
a pipe line raster imag processor
a number of separ imag
a decompressor
a data path over the bu between the sourc

point addit
the result in a single pipelin stage oper
the end of a divis oper
the adder pipelin a divid circuit
sticki
pipe
overflow quotient bit posit
integ operand
econom storag
convers oper
align the datapath
a seri of carri
a quotient regist
a pair of operand
a normal shift amount from examin of input operand

a larg number
the remot pocket pager
the plural of pager
the pager
the group of pager
the frequenc
the collis of acknowledg transmiss between group
the base
the acknowledg
special algorithm
redund of data bit
recept of the acknowledg messag
pseudo random nois code
phase drift
noisi hop
nois ratio
messag in a noisi environ
low power oper
low power acknowledg
low cost manufactur
long distanc
infrastructur
group with each group
frequency-hop spread spectrum differenti bi phase shift
frequenc in a rapid fashion
frequenc hop spread spectrum digit data
frequenc drift
each frequenc hop
digit inform
data redund
an acknowledg
an accur narrow band frequenc
a standard page transmitt
a special doubl loop pll synthes
a single geograph area
a separ start locat
a plural of remot page unit
a page
a histori of the frequenc

a b output the output
the tabl output
the slope for interpol
the number of modul in the other direct
the number of modul
the major
the function valu through adder
the compon in the modul
the binari function oper
the 4 least signific bit in multipli
spiral data path
signific 8 bit
programm
variabl of data type
the grammar of the high level languag
the data type
languag syntax
languag sequenc
languag instruct
languag data type
integ load
instruct type in a comput languag a input
data type variou element
data type
a high level languag
modul of the next column of the array of modul
modul in the next column
interconnect modul in a column of a two dimension array
input selector
dimens
the object in a frame of visual
two dimension imag of that object
the synthesi of imag
the serial process of the pipelin type of the paramet
the screen from a perspect view
the plane of visual
the paramet of the segment
the paramet of the polygon the paramet of the pixel
the paramet of a set of segment
the n pixel of a line of visual
the intersect of the set of polygon with each line of visual of the visual display devic
store paramet of depth
processor for the elimin
previou convers of the paramet of the polygon
pipelin organ
paramet of pixel on a display screen
new one
n block
input for paramet of convex polygon
color paramet
a visual display devic
a valid element
a processor of imag of object
a plural of segment
a further variant
a decrementor
a circuit for the convers of the paramet of polygon into paramet of segment
convolv
b input
an output selector
a output of the neighborhood comparison oper
a output
a neighborhood comparison oper
a function valu
a differ row
a binari function oper

a b tree data structur
valid entri of the tlb
valid entri in the tlb
these entri
the translat tabl i
the translat tabl
the output address
the content of that entri
that entri
no multipl tlb entri for the same input address
multipl address translat in a comput system
more valid entri of the tlb store a translat
more translat for other input address
lookasid buffer
input address
address translat in a comput system
a translat for the particular input address
a particular input address

the sort processor
sort processor

a back end intern storag for the respect sort core portion
the sort core portion
the local memori
sort data
sort core portion
part of the front end
output the merg sort result
extern memori for the respect sort core portion
each sort processor
back end intern storag a an altern memori
back end intern storag
a pipelin fashion
a front end intern storag
a faulti area

the interrupt instruct
interrupt instruct

a backout latch
uniqu regist
the content of uniqu regist
the content of the backout latch
the backout logic use
the backout
state inform in a multi execut unit processor
backout logic i
addit logic in both execut unit of a dual execut unit
a cancel signal i

a backplan
transmiss of atm cell across the backplan
the event a sourc lan
the destin modul
the atm switch backplan
such packet
standard
recept of the atm cell off the backplan
pipelin architectur for an atm switch backplan
ownership of the backplan data
ownership of the backplan
hub
ethernet packet
each lan
cell slot until such time
cell slot
capac of the autonom modul
autonom switch activ
atm cell
an ethernet lan modul
an autonom switch modul
an asynchron transfer mode
a sourc lan
a plural of lan
a destin modul
a destin lan

a backproject algorithm
transfer data between the cpu
the vme interfac
the pipelin oper
the forward projector/backprojector
the dimm daughtercard
the array of asic
pipelin result after complet of consecut pipelin oper
pipelin result
output memori bank
forward project
each asic
doubl buffer memori
daughtercard
data subject
consecut pipelin oper
bank of the doubl buffer memori data
backproject processor
an output memori
an output buffer memori
an array of asic
a vme interfac
a peripher compon interconnect
a forward projector/backprojector
a forward project algorithm
a dual in line memori modul
a ct scanner

the task of remot commun
the system throughput
select intern format
multimedia manag
bandwidth adapt
applic control
a smart memori element

a band width manag function
voic
the multimedia articl
text
system architectur for multimedia commun
multipl incompat video
motion video
hdtv
wide rang of real time
video signal process function for applic
video instruct set
unix applic
univers video
transfer block of video data
these novel visc microprocessor
the evolut of a pluriti gener of the visc microprocessor
scalabl formatt element
real time visc
os2
oper system element
nt
novel architectur
multimedia commun
microblock subimag
macintosh
inter oper arbitrari extern video format
embodo
do
concurr execut of the applic program
cisc co processor element in order
circuit system
a real time object
a real time frame differenti bit map
edtv
h
the program count by m at a time
the parallel process apparatu turn
the parallel process apparatu make great account of compat of a great part of softwar
the k th instruct
the k th branch instruct
that instruct in an arithmet unit
th instruct
success process of convent softwar
success process mode
state flag
state discrimin flag
state discrimin
parallel process for new softwar
m th instruct
kind
instruct of address
exercis parallel process over m instruct in m arithmet unit
execut of instruct of address nm
decod the m instruct
check whether a branch instruct
branch destin
a parallel process apparatu turn
a discrimin changeov instruct
differ video
avail band width
algorithm signal
a plural of control function for commun of multimedia articl
a frame memori system

unit with target cach
the x86 instruct
the bpu
a target cach

a bank
the state of the bank
the low block of a prefetch request
the low block address
the high block address
split block of 8
respect bank of the target cach
low/high
high block address
either bank of the target cach
each prefetch request
an 8 byte align
a split block
a prefetch block
a low block address

a synchron memori devic
the memori section
the extern system frequenc
the column decod
row in plural memori section
row decod
intern oper
control input
column decod
column address for each memori section
a row address buffer

a column
a row

a bank of memori cell
uniqu column
the total number of latch circuit
the memori devic pipelin
the memori cell column
the column
memori array access signal
clock frequenc

a bank of parallel processor
two dimension imag transform
the visual block artifact
the mlt processor
the mlt method
the input data stream
practic vlsi implement
pipelin mlt architectur
number of multipli
multipli add logic for fast comput
most dct base compress system
mlt processor
mlt implement
forward
fast block
dimension mlt architectur
decompress system
dct imag compress system
capabl of wavelet
architectur for imag compress
an infinit impuls respons filter
a product of the mlt window function
a modular architectur

a bank select output
the time of miss signal
the tag translat
the same time a an address
the number of match line
the later condit
the former
the featur of the invent
the data memori of the cach
the bank
separ dynam nor gate
right bank hit
possibl outcom from the compar
path for discharg
output node of the nor gate
no match bit
neither data item
multibit match indic
match indic
low order address
larg part
higher level of associ
fast tag compar
each tag store
delay element in the bank
current limit
clock edg
both bank
bit for each tag bit in each tag store
bit by bit tag
bank selector for a set associ cach in a comput system
bank hit
an exampl embodi
a tag store for each bank
a tag compar
a possibl ambigu
a nor gate output
a minimum time
a memori cycl
a flow through design

a barrel rotat
thi sum result in half a mani partial sum
these larger partial sum
these larg partial sum
the third input
the sum of data in plural equal section of a single data word
the single data word at a first input
the single data word
the origin single data word
the mask block altern section
single data word at a second input
single data word
proper select of the mask
plural section of a single data word
origin section of the data word
larger partial sum
input arithmet logic unit
field addit
embodi thi techniqu
boolean combin
altern section
adjac section of the origin data word
addit in a single cycl
a whole data word basi without ani overflow

a barrel shifter
two dimension gener
the two dimension data
the intern data memori
output data memori address
number of step at a high process
interrupt process
intern data memori
instruct execut pipelin stage
barrel shifter
arithmet process
an extern data memori for an instruct execut stage
an arithmet unit for the execut stage
a write/accumul stage
a round off/accumul adder
a dma transfer
a dma control unit
a digit signal processor of a simple circuit configur

a barrel shifter unit
the tag decod in parallel with bit for normal
the state machin output
the format convert
the decompressor unit
the decompress unit
stream of triangle data
position/color processor
point accuraci
output from the normal processor
output from the barrel shifter unit
instruct in the data stream
input block output
huffman tabl that output
an input fifo
an input block state machin
an input block
a tradit render pipelin
a tag decod
a position/color processor
a normal processor
a format convert
a data path control

a processor architectur
the result of execut of all instruct
the initi instruct
the begin of a branch
the basi of depend
the actual data
provision storag
other instruct depend
invalid on the basi of the depend
instruct execut function by a dynam regist file
free run mode
execut of previou instruct in such branch
comput effici
all subsequ instruct in such branch

a base address
thi first microinstruct
the secondari address
the destin address
methodologi
static delay line loop circuitri
select clock gener mode
other programm regist
control point
clock gener mode between phase lock loop
an intern bond wire option
access pin
a boundari test scan control point
execut of condit depend instruct
a success stage
a secondari address
a second microinstruct in the memori
a first microinstruct
a destin address in respons
a condit depend instruct over a plural of execut stage in a microprocessor

a base address in extern memori of patch code
the row line
the rom data
the rom
the ram cell
the patch code region of extern memori
the patch code region
the overflow region
the end of the row line
rom with ram valid bit
rom code updat from extern memori
rom cell
multipl instruct patche
instruct at the rom
fine granular of code updat
base address
a single rom instruct
a single patch instruct in extern memori
a row of rom cell
a ram cell
a patch code overflow region of extern memori
a column of static ram cell

a base data processor
the base processor
sequenti main memori address
precis indic of error condit for recoveri
expansion/contract of operand in the vector
except inform
except indic through the vector

a directori
the main memori unit until subsequ transact
the cach unit on a so call store into basi
such return
separ oper
searche
part cach
more secondari concurr use with the secondari use
instruct data while the other i
each cach unit
data array
a data array with the directori

a base modul through a messag level interfac
the receipt of an i/o descriptor command
the main system of the complet
the main host system
the main host comput
the host comput system
the base modul
reconnect
program disk
processor with a common backplan
processor in the base modul
processor by the host system
peripher termin unit
mainten
the old file with a temporari name
version of the current oper system
the system mainten
the system access
the request for the new file
the new set of file in the directori
the new set of file
the new name of the new set of file
system mainten on a comput
system mainten by usag of temporari filenam in an alia
new file with a new name in the alia
function compat
each file within the new set of file
each file in the set of old file in the directori
an alia
adequ space for a set of new file
adequ space
access by ani other file
a temporari name
a set of file
a new name within the directori
a file request
incomplet
i/o subsystem
function of a main host comput
error oper of the system
diagnost function for the data
complet of the data
an input output subsystem
a specif peripher termin unit
a result descriptor
a mainten card
a distribut control card
a descriptor link

multipl entri
the possibl of prior data
the opposit section
the interact
the core
program order with the write of data
memori until such time a the cach
memori in program order
cross depend tabl
circular buffer section

the translat lookasid buffer
the predict translat
the multipl entri
the effect address gener
the base operand
set of associ entri
predict translat of a data
number of consecut page
effect address gener
bit of the base operand for select of a set of entri
associ manner
an input address
a system in accord with the present invent
a set of entri in the translat lookasid buffer in respons
a multipl number of entri
a base operand regist
a base operand for the predict translat

a base regist in simd mode
vlsi embodi with an architectur
thi execut
the simd mode
the optim kind of parallel
the coupl
the allnod switch
sisd mode
sisd
simd
sequenti comput
mimd mode
mimd capabl the processor
maximum memori
instruct by instruct level basi
group of unit
element through the interconnect network
element logic
dynam multi mode parallel process array
dynam mode assign
dynam mode
cycl time usag
coupl multipl processor
complier
common resourc
broadcast of instruct
applic at the limit of memori cycl time
altern path a system
a simd mode
a program for the comput system
a parallel risc comput system
a multi mode dynam multi mode parallel processor array
a few cycl for mani mani processor

a base station commun with a plural of mobil station over a cellular network
the signal processor string
the signal processor architectur
the signal process array
the seri processor
the parallel processor string
the mobil station
that inform by an effici task base pipelin
tdma time slot
task base alloc
spectrum commun network signal processor
signal processor element
parallel signal process element
outbound inform
inbound inform from the mobil station
global system for mobil commun
criteria
both seri
a specif task
a signal processor array
a plural of signal processor element
a plural of signal process string

a base station receiv in a cellular commun system by a demodul
multi processor demodul for digit cellular base station
maxim ratio combin for divers path
demodul procedur
demodul
the valu of a control paramet
the phase output
the phase control signal
the output data stream
the filter 23
the data rate
the current phase relationship between the input data stream
the coeffici in respons
symbol
the number of bit in a word
the individu bit of each word
that bin
sequenc among a plural
multipart memori
fewer port
error free result
bin in the memori array
an array of memori cell
a set of bit
a plural of bin
a numer error limit k
a number of error
part of a data modul
oscil 67
modem design
filter coeffici valu
arbitrari frequenc
an oscil frequenc
a multipl of the frequenc of the other data
a digit to analog convert
a digit filter 23
an mlse equal

a sourc program
the translat unit
the stack size
the regist name from the file
the process of each subroutin
the name of a regist
the name
the machin instruct sequenc
the link unit
the determin unit
the branch target subroutin
the branch instruct with an instruct
machin instruct sequenc
high speed execut of subroutin branch instruct
each subroutin
differ file
an acquisit unit
a translat unit
a subroutin call instruct gener unit
a stack reserv
a machin instruct sequenc
a link unit
a file detect unit
a file
a determin unit
a branch oper
a branch instruct from the machin instruct sequenc
a branch instruct detect unit

a basic block of assembl instruct
the microoper of the sourc program
the microoper
the field of the assembl instruct
the assembl instruct
microoper
each other with regard
compil system
assembl sourc program
assembl instruct
anoth assembl instruct
a target program for use in a digit signal processor
a tail portion of the basic block
a head portion of the basic block
a compil system

the transduc
the proxim end
the distal coronari vessel with ultrason puls
the bodi
small coronari vessel
method for use
method for the use an manufactur
member with a distal end
member
intravascular
bodi while a proxim end
a transduc
a small vessel of a patient
a proxim end
a motor
a distal end
a devic for ultrason imag

a pair
the spatial transform processor
the second imag
the pair of imag
the pair
the final imag warp transform
the exact match locat of a second group
the differ imag
polylater techniqu
point on the pair of imag
point a the vertric of the polylater
photoequ
imag registr
imag correl
imag by a photoequ processor
ani dissimilar between the first imag
a supervisori gener purpos processor
a squar root
a special purpos pipelin digit comput
a spatial transform pipelin processor
a number of special purpos pipelin processor
a initi imag warp transform
a geometr pattern
a dot product processor
a differ imag

a basic capacit pressur transduc
thi ac amplifi signal i
the exhaust manifold
the engin
the driver of engin
the compar output
the car
plate
the outer edg
the open slit area
the insid area
the articl by suction on the outer edg
the articl
respect outer edg
parallel plate
form an open slit area between the outer edg
area between respect central portion
a transport devic
a suction devic
output in turn
misfir detect in automobil engin
inexpens automobil engin
high frequenc ac compon
detect system
dc compon
constant pressur level
conduct layer
capacit block
an oper amplifi
an on off switch
an led alarm
an ac to dc convers
ac output
a variabl exhaust ga
a one shot monost multivibr
a flexibl diaphragm of low mechan hysteresi
a bleeder pipelin

an interrupt
data calcul
the pipelin process
calcul method for motion compens
an amount of distort between a last frame block
amount of calcul through minimum distort
amount of calcul
a repeat process oper at greater conveni
a direct memori access
a current frame

a basic cpu resourc
the gener of the interrupt
the basic cpu resourc
termin method of all asynchron process
process interrupt handler
process depend interrupt factor
interrupt handler process
except in the case
except at the time of the gener of the interrupt
asynchron process
an interrupt handler
an asynchron process unit
an asynchron process
a synchron process unit
a synchron process
a cpu resourc

a basic instruct word length
the data processor of the present invent transfer the content of address regist
program regist
pipelin data processor with arithmetic/log unit
load/stor instruct instruct code
differ kind of calcul in a pipelin stage
basic arithmet instruct between regist
arithmetic/log unit
address calcul

a basic macroprocessor
the system through regular system regist
the system organ
the size
the result of the current instruct
the full instruct set of the system
the control line buse
the basic system
success
small scale data
real time system
particular need
overlap of microprocessor function
overlap between instruct execut
other monitor
microprocessor system of the type
memori capabl without ani chang in the data buse
manipul instruct
intern chang in the unit
instruct divers
input/output hardwar
industri process control applic
industri process control
fast pipelin
digit comput apparatu oper with jump instruct
control applic
capabl of the system
artifici delay
ani time
ani system function
addit memori
a small number of regist
a read write memori
a read onli memori
a mainten panel
a direct memori access unit
a design regist
a byte
a basic microprocessor system

a basic signal process part
variou type of signal
these part
the type of signal process
the programm logic part from an extern memori through a data input/output line
the circuit configur data
the bu under control of the basic signal process part
sever differ type of signal processing
programm digit signal processor
circuit configur data
an audio signal
a programm logic part
a plural of signal processing

a beam
the reflect portion
the posit of the retro reflect target
the beam
self align sewer pipe laser
light in the gener direct of the pipelin
individu section of pipe
beam
a retro reflect portion
a reflect of the beam

the instruct bit
the instruct at rate
the fifo buffer
pipelin retriev such entri from the fifo buffer
logic array
instruct segment
bit into a fifo buffer
anoth method
a plural of such entri
a link between success instruct

a beam of coher light with an imag of the object
type of zone
transform digital/opt process system
the inspect
the digit video imag
the data for each wedg
ring
the simd processor
the regist file unit
the regist file input
the processor element within an simd processor
slave control unit
simd processor through interfac unit
set of processor element
right
tri state output
programm arithmet logic unit
dual input port
data in either port
conjunct with a fast microprogram store program memori
cmos/so technologi
an operand between devic input
an lsi compon
a programm arithmet logic unit
respect one
plural processor cell
pipelin array
parallel reconfigur comput architectur for robot comput
output data in synchron with a minor cycl clock under control
one of the regist file unit
ensembl of plural processor
a plural of regist file unit
a particular minor clock cycl
a master control unit
a larg number of single instruct multipl data
other well known
other comparison purpos
other characterist for comparison
optic gener
dimension object
dimension buffer
digit optic process system
data valu
coher light beam
an imag for inspect
a neural network type processor
a digit video imag of an object

a beamform control system
the signal nomin center frequenc
the secondari control
the rang spatial resolut
the present beamform control system
the number of beam
the final valu by the primari control
the beamform control system
synthet apertur oper
secondari control so that delay
multipl simultan beam oper
multi process channel of the beamform system
focu control
data set
beamform system
beamform
beam to beam adjust frequenc
base delay
apod data set
apod beamform profil
all beamform system
adapt beamform
a primari control

a behavior specif
the list of statement into statement block
the list of statement from each statement block
the control structur templat
the behavior specif
each statement block into a control block
each cluster into a control element
control structur templat
a control structur templat
a control structur
a control element templat

a benchmark program
trace
the trace file effect address
the trace file
the processor perform statist
the processor model
the processor design perform
the op code of the instruct
the benchmark program
small segment of contigu trace instruct
execut driven simul
each output instruct of the trace file
each instruct in the trace file
decis control transfer instruct
averag cycl per instruct
addit for memori access instruct
actual branch destin
a trace file
a memori model

a best match
variou codevector vcb
the respect codevector
the number of codevector
the lowest distort
the dmc
the codevector
the bmag circuit
the avq
norm
the data vector
storag line of a cach memori
privat storag column in the cach memori
parallel comput processor
norm calcul
element access data
coupl
the smart debug interfac circuit of the present invent
the programm digit processor
the interfac port coupl the smart debug interfac circuit
the interfac port
the instruct regist coupl
the control logic circuit interfac
the control logic circuit
smart debug interfac circuit
program with the programm digit processor
program on the host comput system
instruct onto the instruct
data from the data
boundari scan bu delay on the instruct
an interfac port
a softwar applic for a programm digit processor system
a softwar applic for a programm digit processor devic
a smart debug interfac circuit for the diagnost test
a programm digit processor
a parallel manner
a control logic circuit
a term
a parallel comput processor
measur of the distort between vinput
each dmc
codevector
applic for the avq
analog switch capacitor vector quantiz
an identif
a vector input signal vinput of input signal sample
a switch capacitor implement of an analog vector quantiz
a plural of distort

a bi direct commun mode
westward transmiss of data through the row direct commun line
west
way data transmiss from west
way data transmiss
the unidirect commun mode
the row direct commun line
the network control unit
the column direct commun line
the bi direct commun mode
southward transmiss of data through the column direct commun line
row direct commun line
parallel comput system with error
east i
data driven processor
commun control mode
column direct commun line
a unidirect commun mode
a tauru mesh network
a parallel comput system
a network control unit

a bi direct data pipelin
the run length count tag
the run length count regist
the run length count into the run length count regist
the run length count from data byte in the fifo
the dma buffer
the data byte
system develop tool
success ident data byte
second hold regist
pipelin element
ident byte
each success ident byte
each success clock cycl
dma buffer
data compress for parallel port interfac
data byte of the data word
data byte
a run length count regist
a memori with a commun port
a fifo for transmiss over the data path

fall time
xor
xnor
wave pipelin system
pull down transistor
output state transit
not invert function
nor
nand
high qualiti one
everi combin of input state transit
equal rise
equal delay
each circuit
complementari transmiss gate
cfet logic circuit

a bia
variou semiconductor technologi
uniti
the time rate of chang of the effect load
the state of the circuit output
the state of the circuit by the use of time delay neg feedback
the logic swing of the circuit
the load devic
the effect load
symmetr rise
primari use in vlsi logic circuit
particular circuit implement
mani other
low voltag
low power at high switch speed
logic signal swing
ideal bia voltag with a voltag follow type circuit
finit delay
cml circuit
analog circuit
an effect load
altern circuit configur
activ load devic
a gain

a bidirect data
thi bu carri both instructon
the separ data
the risc processor
the processor input instruct
the novel interfac
the implement of featur
the bidirect data bu
statu report
processor output address
processor output
instruct transfer
instruct signal
instruct buse
independ buse
high transfer rate at a reason cost
high perform processor interfac between a single chip processor
data access signal
coupl the processor
concurr data
chip memori
burst mode processor protocol with the burst mode protocol
bu structur
bu statu
address bu
a signal path
a set of devic
a processor input instruct
a high perform interfac between a processor

a bidirect data bu transfer data from the buffer
the transfer between the buffer
the end of the segment
the data transfer
the current program segment
the bidirect data bu transfer the result of an alu oper
segment by segment
intern task request
harvard architectur microprocessor with arithmet oper
control task for data
all necessari data transfer for a two address oper of the alu
a unidirect data
a high process
a high clock rate
a central processor for digit signal process

binar
those dark area
the vision processor
the exist of a now isol dark area
the exist of a defect
the defect
the dark area within the imag
the chip in a bright field
surfac inspect
detect of a defect
area in the imag
an articl
a televis camera
a semiconductor chip
a machin vision processor

a binar threshold valu
the multi valu imag data
the multi valu imag
the binar threshold valu
binar of the multi valu imag data
a multi valu imag

a binari compens
the bit number of the multiplicand
the bit number of the multipli
the array circuit
respect partial product
more bit of the product
an integr valu
an array circuit
a real number
a product of a multiplicand
a multiplicand in each bit
a multipli in each bit

a binari convers
use of a least mean squar adapt algorithm
the next convers stage
the binari convers
the analog input
practic circuit nonid
nonid of the a/d convert compon
high level of amplifi nonlinear
gain error
each stage address
digit error correct system
convert with arbitrari number of stage
convers error
common look up tabl
bit per stage
binari signal from the look up tabl
a simple method of calibr for the a/d convert
a residu analog
a gener architectur

a binari data sequenc from an input sequenc of data
viterbi detector
valu in respons
the viterbi circuit
the storag devic output
the input sequenc of data
the detector circuit
look up tabl
all possibl noiseless respons
all possibl input valu
a viterbi circuit
a detector circuit
a binari decis output

a binari map
valu of pellet reflect
the tile boundari
the processor check for coincid of the edg pixel with a nomin edg line
the pixel imag of the pellet
the pellet
the edg of the pellet in the map
sidewal
pellet
nuclear fuel pellet
non contact flaw detect for cylindr nuclear fuel pellet
flaw
edg flaw
edg defect
convolut filter
contrast at the edg
camera sensor element
blob of bad pixel
bad pixel
associ bad pixel
adjac area
a video finit impuls respons filter
a single blob
a seri of modular vme board
a seri of line scan for the pellet
a processor count
a non contact surfac flaw detect system for workpiec
a line scan camera

the other subunit
subunit

a binari number
thi maximum valu
the significand of the result
the signal i
the lza
the exact number
the carri of the addit oper
the addit for the case
point addit oper
normal a a shift amount
non signific digit
non signific binari digit in the significand of the result of an addit
binari digit of the number
anticip
an addit delay
account the maximum valu
a shift
a plural of binari signal
a maximum valu of the number of non signific digit
a few digit

a binari tree
signal pattern
multiply/accumul
input/output for the array
input digit signal sequenc
element with respect
element memori
element input/output
digit signal sequenc pattern
binari tree multiprocessor
array of plural signal process element
and/or through the root

a bit in each instruct cach entri
the slot of the single cach entri
the second integ pipelin
the cach entri
slot of the instruct cach entri
slot control
parallel execut
integ pipelin
emul of complex instruct
each storag locat in the instruct cach
decod the instruct from the compact form
decod instruct
auxiliari inform
a single bit for thi purpos
a second slot
a loader unit

a bit map
the preprocessor
the portion of each quadrilater edg in each swath
the bit map
system for a pattern gener
swath
set of beam processor
separ vector
pattern gener
laser
edg vector
each quadrilater element in a pattern
account rel movement between the laser scanner
a real time processor

a bit map represent of the entir target
the time of pixel comparison of ideal with real pattern
the target pixel
the stage posit
the inspect system
substag illumin with non laser light
strip
right vector represent
pixel represent
orient the target
onli guardband inform
more polygon
laser beam in focu on the target
larger target area
interferomet
inspect a pattern on a target on a stage
inspect
ic bar
guardband around polygon side
guardband
glass scale encod
fiduci mark
each ic bar
data descript
an ideal pattern
an autofocu keep
align mark
actual target area
a turnpoint polygon represent
a single data
a laser pattern inspect and/or
a databas
a consolid
writer
system for pattern inspector
defect area
defect area consolid
polygon data represent
pattern compar with substag illumin

a bit of the partial product
the sequenti order
the rca band in each stage
the rca band in each adder stage
the pipelin multipli
the partial product from the partial product
the least signific bit of a next more signific rca band in the adder stage
the carri of the full adder
the carri from the rca band
the adder stage
the accumul partial product
signific full adder in the rca band
signific bit of the partial product
sequenti order
same number of full adder
rca band in the next adder stage
rca band
partial carri save pipelin multipli
next adder stage
last adder stage
each adder stage
band each band
an accumul partial product
a rca band
a plural of ripple carri adder
a plural of full adder
a partial product processor
a partial product of the multiplicand
a next stage
a multiplicand
a more signific rca band in the next adder stage
a half adder

the float point processor
a float point processor

a bit scanner
the sticki signific valu of the smaller operand with an align valu in order
the sticki bit predictor circuit
the sticki bit
the bit scanner
sticki signific valu
sticki bit detector for a float point processor
output circuitri
an expon arithmet circuit
a sticki bit predictor circuit
a sticki bit
a mantissa arithmet logic circuit

a bit serial processor
transpos
the word orient processor
the transpos convert serial input
the bit serial processor
the bit serial input of the transpos
the advantag of an array of bit serial processor
readi commun between data
n bit serial input
more transpos
m bit parallel output
each bit serial input of the transpos
connect with each word orient processor
bit serial parallel processor
bit serial fashion
an array of word orient processor
a plural of word orient processor
a memori for each bit serial processor

a bit shifter
a multipl accumul
a divis with the use of a clamp valu

a bit stream output in the form of x y coordin
video buffer
the system featur host comput
the pe in the system
the optimum for the job
the next peg
the implementor configur simple network of pe within peg
the implementor configur pe
the bc
subassembli
straighforward pipelin configur
simple job
pipelin of cage
pel
pe within the peg
pe from other peg
network choic without massiv invest in memori
myriad imag
logic invert
job
full variabl connect within the peg
extern pe connect
element group
each peg
each cage
configur parallel pipelin imag
capabl with little addit structur
cage exit mecham
cage connect
bu connect
bu capac
boolean combin imag switche
bit stream input
binari window processor
bc output
bc input within the pe
an array of peg
an addit feedback loop
addit switch path
a compound bu connect network within the cage

a bit width
unit iu in a microprocessor
unit iu
the shortest instruct
the second instruct decod
the non shortest instruct
the erron inform
shortest instruct
second instruct of the shortest instruct
result of the second instruct decod
result of the second decod in the case
instruct in parallel
i the non head code of the instruct
first instruct
a second instruct decod
a pipelin control unit pcnt invalid
a first instruct decod

a black refer clamp
the pre processor circuit
the pre process function
the imag signal
signal improv
right shift
real time digit processor
multi color imag sensor
lumin interpol circuit in linear space
lumin
logarithm space
log space for white balanc
linear space
interpol
hue signal
full resolut color signal from a multi color imag sensor
correct into an applic depend post process phase
color signal in a real time system
chromin signal
chromin interpol
chroma
blue signal
a signle
a digit process system
a defect conceal circuit
a color separ

a blit engin modul
variou modul
unread data
the low threshold valu
the low prioriti request
the high threshold valu
the high prioriti request
the fifo with display data
the fifo mug
the fifo data
the earliest time
the dram control sequenc
the display fifo modul issue
the display fifo modul
the display devic
request for memori access
priorit request for dram access
low threshold valu
high threshold valu
high prioriti request for dram access
fifo underrun
a high prioriti request
a half frame buffer logic modul
a dram control sequenc
a display pipelin
a display fifo modul for use in dram interfac

a block bit
request bit
queue entri
cach coher in a comput system
a sleep bit

a block end address
the oper of the data
the memori with the content of the program regist
the control signal from the instruct
the content of the program regist with a data
the content of the program regist
the content of the block start regist
the block start regist
the block start address
the block instruct by the instruct
devic within each instruct cycl
block instruct in a data processor
assert of address
a start address for a block of instruct
a program sequenc circuit
a program regist
a pipelin organ
a block start regist
a block sequenc
a block instruct
a block handler unit

a block match method
type of motion
the number of candid block of the previou frame of the imag signal be
the motion vector at the odd number field
the motion vector at the frame
the motion vector at the even number field
number of pixel data
n pixel
imag signal process circuit
frame unit of an imag
detect of motion vector
circuit for detect of a motion vector
an imag data
a search over all frame of the imag
a plural of block
a block size of a refer block of a current frame of the imag

the physic cach unit
the logic data cach
the logic cach
further aspect of the comput
either main memori
data without the necess
data at logic address
an input/output processor
a physic cach unit
an address translat unit
an address scalar unit
a vector control unit

a block of operand from the central processor
the tag store
the tag of physic address
the operand for deliveri
the memori control unit 22
the block of operand
subsequ deliveri
store operand in a data cach
receipt from the control processor
physic cach unit for comput
inputs/output processor
clock cycl in tag store

a block of target instruct
the target from the branch
the program at a locat
the point in the program
the opcod
penalti in the execut of a program sequenc of instruct
instruct prefetch mechan
instruct for better util
an indic of the size of the block of target instruct
a trace vector of a path in the program sequenc
a target address of the branch

a block processor
the machin level oper
the decomposit unit
the block processor
machin languag oper on comput block of data
extern suppli primit command packet
doubl buffer local zone memori
data from burst access block of data
block oper on comput block of data
architectur for block
align circuitri
address signal
a macropipelin
a decomposit unit

a block transfer mode
the rest of the multipl data
the data of the address
the block transfer mode
system with simultan initi transfer of target data
multipl data from the memori system
intern process
cach in parallel from the memori system
access a memori system
a cpu read access request for a single data

a blurb
write request packet
these control line
the pipelin length
the particular request
the messag type
the messag gener
the messag control
the memori bu i a packet orient bu
the length of the pipelin
the length of a pipelin
the intersect of these line
the differ messag
the data portion of the bu
request messag
request in the bu pipelin
read request packet
processor modul
processor buse
possibl error condit
pariti check bit
more bu transmiss slot
messag gener
memori request from a processor modul
memori control unit
interfac for use between a memori
end of the messag
each slot in a packet
compon of a modul
bu monitor
ani further request
an mcu node
accord with a specif control protocol
a three level pipelin mode
a seri of messag
a particular request in the pipelin posit
a number of intellig bu interfac unit
a messag control
a matrix of orthogon line
a bu interfac unit node

the state of the microprocessor at the time of the fault chang
the state of the microprocessor
the processor interfac chip
the microprocessor if an error
the mainten diagnost chip
the flow
tandem
physic memori without regard
multipl microprocessor request between the microprocessor
memori locat for boot code
inform over a processor
evid of the caus of the fault
data befor a microprocessor
a secondari cach
a read request
a processor interfac chip
a mainten diagnost chip
a differ state

a boot address reloc
microprocessor interfac
a request pipelin
a prefetch queue

a booth type multipli
wp
thi product wp
the sum of product
the sum in order
the correct binari number for the product wp
row of full adder
row of carri save adder
pipelin activ filter
number of weight
multipli unit for each weight
multipli unit
m multipli unit
less signific multipli posit
each multipli unit
carri save adder/ful adder combin
booth decod
a pipelin activ filter
a kernel array

a bore hole near the pipelin
transit within the pipelin
the signal processor actuat
the pipelin at low pressur
the packer
the interior pipe wall
the insert
the gamma ray detector
the electr analogu
subsequ withdraw of the radiat sourc from the vicin of the pipe
pipelin leak detect method
leak test
leak detect at success locat within the pipelin
intern travel within the pipelin
intern high pressur
high pressur behind the packer
further movement of the unit
energ of the packer
control devic
condit while the packer
a stimulu for the gamma ray detector
a radiat sourc on the surfac
a pipelin packer
a pipelin at select locat in order
a gamma ray detector
a control devic for such unit

a bottleneck in the pipelin
the rapid calcul
the processor in order
the high throughput of the pipelin system
the comput workload
system for a graphic workstat
system for a comput graphic workstat
perspect project
display of high qualiti

a bottom of the interrupt instruct
thi entri
the valu of the non-specul non interrupt tid
that tabl
that order determin
target identifi
oper of the interrupt instruct
instruct buffer entri pointer
an interrupt instruct tabl i
an entri at the bottom of the interrupt instruct tabl i a next instruct
a true specul execut point
a target identifi
a non-specul non interrupt tid

a boundari condit
the self snoop mechan
the processor system bu
own request
other bu agent
initi intern cach lookup
i/o subsystem and/or other processor
determin that the request
commun between the processor
a self snoop mechan
a boundari transact

a boundari of the object
the respect edg of the object
the imag refer frame
respect edg
point in the imag on the boundari
orient of those point
characterist of the object
characterist of an object
center of mass
boxe
box
boundari point
appar boundari point
an object in an imag
an edg of the object
an edg
a function of those boundari point

a branch address
thi way the apparatu
the uncondit branch instruct
the program counter valu of the branch instruct
the operand address
the instruct length of the branch instruct
the address calcul devic
subroutin branch instruct
next instruct address calcul in a pipelin processor
loop control instruct at the instruct
disturb in the pipelin
devic for a data processor
branch target
an address calcul devic
a program counter valu calcul devic

a branch predict cach
thi addit data
the address of the second instruct
the address of the branch instruct
superscalar instruct
instruct length
a parallel process pipelin system

a branch address associ memori
word line
the top of the rtnstack
the return address stack
the return address associ memori
the branch address associ memori monitor
target address associ memori
recent call type instruct
multipl matche in the branch address associ memori
multipl caller
multipl branch address entri for a single return type instruct
branch predict cach with multipl entri for return
a return address associ memori
a branch address cach

a branch address into the program counter in respons
statu condit
set of the statu condit of the circuit
set of the statu condit
oper of the circuit

a branch address stack
the valu of the pc
the result of comparison
the effici of instruct branch oper
the coincid
the branch point address
the branch point
the branch oper
pair of branch point address
address from the valu of the pc
a pair of a branch target address
a branch reserv instruct in advanc of the branch point in the instruct sequenc
a branch reserv instruct
a branch point address in the stack

a branch delay slot
the branch inform
the address pipelin
an address pipelin

a branch by a branch instruct
thi flag
the queue memori
the instruct in the branch delay slot
the branch instruct till the execut of the branch instruct
the branch delay slot for the branch instruct
parallel process unit
instruct in the same block a a branch instruct
instruct in the block
branch method
an instruct memori into a queue memori
a queue memori
a predict of a branch
a plural of block of storag unit
a parallel process unit

a branch cach memori
the prefetch section
the predict rate of the system
the branch memori in order
the branch cach memori
the branch cach entri throughout the branch cach memori
the address of the micro instruct be
the address of the macro instruct be
result a an address
number of bit
micro instruct bit
macro instruct bit with micro instruct bit
macro instruct bit
interpret
index for branch cach
index for a branch cach for use
index dispers branch cach entri throughout the branch cach memori
branch target addressess
a look ahead fetch system

a branch cach system for use
the prefetch stage
the boundari
that branch instruct
parcel prefetch
parcel boundari
more parcel
more memori set
branch instruct if the align valu
branch cach system with instruct boundari determin
align valu
a plural of memori set

a branch command
variabl delay branch system
uncondit branch command
the readi of condit code
the meet of branch condit
the current instruct sequenc
target instruct into oper a the current instruct
subsequ detect
split command
pipelin content
dual instruct regist
detect of a branch command actuat a regist
current instruct
branch jump with consider time saving by effect program
anoth branch command
an interv of delay
a split command
a sequenc of target instruct
a pipelin comput
a pipelin break
a condit branch command

a branch condit a a normal instruct operand
trap address
thi delay branch method
the single cycl of the pipelin
the condit bit
the branch instruct in the pipelin
subroutin
tree entri
track of the possibl flow path
the flow of the program
the filter cach
the code pump
possibl instruct stream
instruct from the memori
instruct from all possibl stream
instruct from all flow path
flow path
dealloc ani entri in the data structur
call
anticipatori instruct transfer interfac with processor side instruct select
a filter cach
a data structur
a combin of multipl stack entri
special handl techniqu
single cycl branch instruct in a pipelin
no replac of the instruct
instruct set comput
effect until the next follow instruct
condit branch in a single processor cycl
a special case within a separ condit code regist
a simple circuit

an n stage pipelin
the valid
the execut of an invalid instruct
instruct word from a memori
data segment
a fault condit

a branch condit of a condit branch instruct
the state of the result of the oper
the result flag a data
the result flag
the pre read result flag determin
the pre read result flag
the intern state of the processor
the instruct fetch address gener portion
the execut portion
the complet of the oper
the branch condit of the condit branch instruct
an oper on input data
an intern state regist
an instruct fetch address gener portion
an execut portion
a result flag
a pre read result flag determin
a pre read result flag

a branch control
the tag in a plural of stage
the settlement of condit code for condit branch instruct
the respect stage
pipelin tag
instruct at the respect stage
differ stage
condit branch instruct in pipelin process
condit branch instruct in a pipelin process

a branch control unit
the programm visibl state of the comput
the outcom of the condit evalu of such condit jump oper
the oper of the comput
the instruct issue pipelin
the effect of unsuccess oper
program flow control oper
process comput oper
path inform
condit jump oper
an arbitrari set of path
a vliw processor
a single path
a larg number of parallel function unit
a form of look ahead comput after a condit branch
a field in the oper
a correct path

a branch destin address
the next address
the instruct field of the instruct block
the instruct block
the branch instruct field of the instruct block
the branch instruct field
the branch instruct execut unit
the branch destin address on the basi of the content of the operand
the address gener circuit
instruct field
branch instruct field
an instruct block
a plural of instruct in parallel without no branch delay
a next address of an instruct
a instruct block
a branch instruct execut unit

a branch execut unit instruct
thi short backward branch loop
the short backward branch loop
the short backward branch instruct
the second iter
the method store
success iter of a short backward branch loop in a single cycl
set of the execut unit instruct
method embodi
certain one the plural of clock cycl
a target execut unit instruct
a short backward branch loop of execut unit instruct
a short backward branch loop
a short backward branch instruct
a second iter
a plural of iter of the short backward branch loop of execut unit instruct over a plural of clock cycl
a first iter

a branch instruct in the microprocessor
the next linear instruct pointer
the microprocessor state inform
the front end microprocessor pipelin
the branch ip
some processor state inform
inform about the branch instruct
execut at the next linear instruct pointer
execut at a final branch target address
execut along the current path
branch outcom for the branch instruct
a branch instruct pointer

a branch instruct type
the pre fetch address
target address in return buffer
system for return from subroutin
output from the buffer
branch type inform in bht
branch histori inform in a branch instruct buffer
an uncondit branch instruct
an address of a branch instruct
a return buffer
a return address for a return from a subroutin
a look up oper

a branch mask
the specif condit code
the earli determin of the condit code
the earli condit code
the digit subterm
the determinist condit code analysi mechan of the present invent
the condit code subterm
subterm comput
select subterm combin earli condit code analysi mechan
select subterm combin
normal execut of a condit code
inclus of the branch decis mask a a subterm
determinist earli condit code analysi
condit code by the gener of digit subterm of the operand data
central processor architectur
branch decis analysi
a wide varieti of condit code
a central processor architectur

a branch memori
two step branch oper with second oper rel target address
the target instruct in the line
the line in the instruct memori
the branch predict entri
the branch instruct in the line
normal sequenti oper
each branch predict entri
circuit load the target address into the counter
circuit invalid ani instruct
circuit increment the address valu in the counter
an address valu
a target address of a line
a sourc field
a plural of line of a plural of instruct
a plural of branch predict entri
a branch target field

a branch oper while the other
the address of the branch
the address of a command
special bu cycl
oper in a comput system

a branch predict bit
the instrument
the execut program
the branch statist
that bit
statist
correct branch predict a major of the time
branch select statist
branch predict in an execut comput program
a standard trace program
a major of the time for the workload

a branch predict circuit
the branch predict circuit
target instruct prefetch cach
flow of instruct
execut pipelin a target instruct
an instruct pointer gener
an execut pipelin

a branch predict method
way the next occurr of thi branch
the histori
not taken histori of branch opcod

a branch predict scheme
weak state
the target cach store
the histori cach store histori inform
the histori cach
the exemplari embodi
onli stori a single histori bit
not taken branche
histori cach
a two bit predict algorithm
a separ histori cach

a branch predict tabl i
the risc architectur class of workstat
the purg
the outcom of branch instruct subject
the effici use of pipelin
the branch address under consider
reload
rate of modern comput
practic
execut in a multipl processor digit comput
erron predict
correl base branch predict in digit comput
combin of outcom from prior branche
accur predict of branch instruct
a popular techniqu
a correl between a histori of success prior branche

a branch procedur
the prefetch unit into branch target address
the other procedur
the execut of the branch procedur
the branch procedur
branch instruct interlock
anoth procedur
an execut of the other procedur
an execut of the branch procedur
a prefetch unit prefetch instruct from memori

a branch recoveri mechan
the locat of the branch instruct
store of the instruct
store of instruct
an incorrect branch predict in a processor

a branch resolv
valid bit for the instruct in the pipelin
thi regist
the sum of a base address
the sequenti address regist
the length of the instruct for complex instruct set
the last instruct in the pipelin
the instruct length for instruct
the instruct fetcher
the adjust valu
the address of the last instruct
the address of a branch instruct
oldest instruct in the pipelin
instruct stream discontinu
instruct in a super scalar processor
branch resolut in a processor with multipl execut pipelin
ani pipelin stage
an adjust valu
a sequenti address regist in the last stage of the processor
a recoveri address for branch
a pipelin valid array

a branch tag
the return stack storag
the return predict unit upon detect of a branch mispredict
the result of the comparison
the mispredict
the content of the return stack storag with respect
the call tag
return tag
return instruct
return address for return instruct
pipelin of the microprocessor
a stack structur
a return tag with each return address
a return stack storag
a call tag

a branch target
the read branch target inform
the instruct at each place
the first loop exclus instruct in the branch target
the entri of the loop
the entri of a loop
the branch target storag unit
the branch target inform
second loop exclus instruct
judg
inform of loop
branch target inform of an instruct
a second loop exclus instruct
a high speed loop
a first loop exclus instruct
a branch target storag

a branch target address of the predict branch
the sequenti instruct address
the predict branch instruct
the predict branch
the instruct output from the instruct
the counter section
the branch target address of the predict branch instruct in accord with a comparison result
synchron with an increment of the program
success after the predict branch instruct
pipelin processsor
address a a sequenti instruct
a predict branch instruct
a counter section
a control flow
a branch target address regist

a branch target gener
the btb with a pc output
branch target buffer updat
branch predict system
a predict index
a lower part
a linker

a branch target instruct in the program
the storag facil
the instruct interfac
the instruct in pipelin cycl
the instruct from the instruct regist
the file address
the data interfac
set of locat in the instruct memori
sequenti instruct address
process within the program
port under program control
instruct processor process data in respons
instruct in pipelin cycl
instruct from the instruct memori
file address
dynam alloc of the file of data locat
data in a file of data locat
an instruct prefetch buffer
an instruct interfac
an address interfac
a storag facil
a simple single access mode
a data interfac

a branch target selector
the prologu period of a next inner loop
the loop paramet
simple constraint
prologu
multiway control transfer
overlap between the epilogu period
outer loop code
multi way control transfer
loop state
loop perform
loop bodi code
garbag oper
certain class of softwar
loop control
loop code
inner loop code
inner loop bodi code
epilogu portion of adjac inner loop
epilogu loop period of adjac inner loop
control transfer address
architectur support for softwar
an implement of loop state
addit code element
a start patch
a set of loop paramet
a finish patch from control transfer address regist in accord with loop state
a compil for execut on a processor
loop control structur
the bodi of a loop
side effect manual control
respect subset of execut unit
predic
the predic
system in a multi processor environ
more memori element
more condit signal
more branch test signal
logic mask
branch test signal
a single take branch
a predic
number of instruct in the loop bodi
loop control logic
loop control in accord with the present invent
load manual control flag
instruct width
inner loop
implement of the power architectur featur
fewer servic function
fewer instruct
execut featur of a vliw architectur
eplogu period of loop in a vliw processor
epilogu loop period
epilogu control
code element
architectur support for execut control of prologu
an epilogu counter field
a loop mode flag
a loop control regist
a current loop counter field

a branch unit in a processor
the updat valu a the complet version valu
the updat valu
the specul execut of instruct
the dispatch version valu with the complet version valu
the dispatch version valu for branch control
occurr
these digit valu
the test signal curv
the test signal
the same valu
the puls
the intern signal delay of the flip flop circuit
the gener of the test signal
the form of digit valu
test purpos
test puls
store address test signal format
signal for the respect data
product specif digit test signal
particular
comput control
a test puls
a puls
a format memori
instruct at address
implement for specul execut of branch on count instruct
dispatch of a condit branch instruct
content of a complet version regist
complet of the branch
complet of initi
an updat valu
a dispatch version valu
a count regist
a complet version valu

a branch verif method
verifi
verif
the perform of superscalar
set of prefetch buffer
multipl clock
distinct pipelin stage
correct instruct
a superscalar comput processor
a multi clock instruct

a breakag locat in cooper
these pressur sensor
the quantiti of flow
the pipelin breakag
the occurr of a seismic earthquak event
system of fluid flow requir
sensor on the basi of a pressur chang of the fluid
respect pressur sensor
pressur sensor
pressur reading
pressur of a fluid
pipelin breakag
more valv in accord
custom demand level
custom
center
breakag of a pipelin network
breakag locat
a pressur sensor
a plural of pressur sensor
a pipelin breakag
a fluid pressur chang
a breakag locat on the basi of inform

a breakpoint except
use with the motorola
the microprocessor in respons
the instruct cmmu return with code instruct
the instruct cmmu
the fault code
the code address
the cmmu
return with a fault code
off chip breakpoint system
instruct address in a processor system of the type
equival address
code address
cmmu
breakpoint regist
breakpoint address in the breakpoint regist
breakpoint address
a fault code

a breakpoint facil for the microprocessor
the store by the microprocessor
the sequenc under control of the microprocessor
single step oper
programm sequench
program segment
oper of the sequenc
microprocessor read/writ
intern compon
halt
the test unit in combin
the microprocessor test interfac
the direct insert of instruct by the tester into the processor
test facil for the single chip microprocessor
step the processor
queue instruct
normal instruct
normal execut
microprocessor test interfac
instruct into the microprocessor under test
gener purpos central process unit
develop of comput system
cpu statu output pin
cpu control input pin
bu structur of the comput system
bu structur of the comput
an extern test unit
a single cycl execut time
a risc environ
a parallel test interfac
connect of an extern microprocessor
conjunct with a program counter portion of the sequenc
a writeabl control store
a single chip microprogramm sequenc
a number of regist
a breakpoint regist

a peripher devic
a synchron dram
the synchron random access memori devic
the synchron random access memori
synchron wrap oper in addit
synchron random access oper
data in a synchron burst oper
a synchron random access memori
a static storag devic
a dynam storag devic

a bridg devic
the peripher devic attempt
the buffler
the bridg devic
termin of the read access
success main memori access from the peripher devic
subsequ memori access request from the peripher devic
specif data portion of the main memori
preemption of the peripher devic
look ahead techniqu
data from the main memori
comput with cach line buffer
comput buse
back oper
back cach
an inter bu buffer

a second input
a first input

a broadcast manner the success set of cone beam measur data
tomograph imag apparatu
the subset of pre calcul imag
the plural of processor
the object with a cone beam radiat sourc
the cone beam measur data broadcast
the cone beam measur data
success set of cone beam measur data
sequenc of success one of the subset of pre calcul imag
second input into radon deriv data for a respect subset of the radon
radon deriv data on a plural of radon
imag reconstruct of a region of interest of an object
effici multiprocessor implement
an exact cone beam imag reconstruct
an area detector
a plural of subset of pre calcul imag

a broadsid compar of the refer address against all address
write through cach capabl
the scalar data cach
the refer address into a cach array address
the plural of scalar regist
the data word in the cach array
the cach array
everi data word in the cach line
each cach frame
data from a common memori into everi data word of a cach line
cach line valid indic
associ scalar data cach with write through capabl for a vector processor
a valid cach line
a scalar data cach in a scalar/vector supercomput
a plural of data word
a plural of cach
a cach load control
a cach line valid compar
a cach line hit indic if a data word
a cach array
a cach accessor

a brush element
the trajectori
the brush
the approach
latter case
array calcul
ani posit
ani point in applic coordin
an insid indic
acceler
a trajectori
a set of object
a refer point
a display pictur
a comput method
a brush object element with a trajectori object element in a graphic

a btb registr discrimin
the main memori at the time of mishit of the instruct cach
the first execut time of the branch instruct
branch predict by btb
branch inform in the btb

a bu access
the memori oper
code segment violat in a comput system
a second signal
a memori oper
a code segment violat

a bu arbitr circuit
the serial port
the link port
the intern memori
the i/o processor of the digit signal processor
the i/o processor access the memori bank on the first bu without interfer on differ clock phase of a clock cycl
the digit signal processor through an extern port
the core processor
second memori bank
second buse
more serial port
more link port for point to point commun with extern devic
memori bank
extern access
each digit signal processor
digit signal comput
data for the digit signal comput
bu architectur for digit signal processor
an i/o processor
an extern bu through the extern port
a region of a global memori space
a processor id
a monolith digit signal processor
a dma control control dma transfer through the extern port
a core processor

a bu arbitr scheme
type of transact
the host modul
the client option signal
the client modul
the bu system
the arbitr signal
inform on the bu at ani time
inform on the bu
each client modul
each arbitr signal processor
control of the bu for a minimum period of time
client modul
arbitr scheme
an earlier cycl
an arbitr signal processor
a plural of client modul
a host modul
a bu system

a bu attach
three dimension graphic imag
the system frame buffer
the minim of bandwidth requir
scanlin
design chang at a minimum
comput system design
approach the bandwidth requir between a system frame buffer
a scanout devic
a scanlin
a hardwar scanlin

a bu bit processor output
transmiss line design consider
tradit comput bu structur
the system card in a convent manner
the subset of comput bu input signal
the set of bu bit processor
the digit gate logic circuit of the bu bit processor
the comput bu input signal
the bu bit processor output signal
the bu bit processor
system card
oper on a subset of the set of comput bu input signal
each bu bit processor
digit gate comput
comput bu structur
comput bu output node
a single line of a tradit comput
a set of comput bu input signal
a set of comput bu input node
a set of bu bit processor output signal
a set of bu bit processor
a digit gate logic circuit
a comput bu

the card
the bu convers devic
protocol of the system
protocol of the processor
protocol of the comput system
other agent
cach coher control
bu lock convers
bu arbitr convers

a bu bridg convers devic
the processor card
insert into a slot of the comput system
a varieti of processor type
a univers architectur
a processor card

a bu bridg convers devic for insert into a slot of a host comput system
processor subsystem for use with a univers comput architectur
a processor subsystem

a bu control control access
the first bu request
the bu request from the other bu request
each bu request
bu request from a first bu request
arbitr mechan
arbitr decis on plural bu request from each bu request
arbitr between the first bu request in parallel with the gener of the second bu request by the bu request
a second bu request
a plural of bu request with a comput
a plural of bu request
a first bu request from each bu request

a bu control unit
the number of the intern bu line
the number of intern bu line
the bidirect intern address bu i
second buffer for an instruct cach
invalid
xbar interfac
the perform of the xbar interfac
the design of the multiprocessor element
the band pass
point to point architectur
obsolet data within cach memori in a multiprocessor architectur
master system storag control
less multiprocessor
intermedi level cach modul
individu instruct processor
increas in interfac
connect cost
cach resourc
cach coher scheme for xbar storag structur
attend perform advantag
a larg number of multiprocessor
an intern address
address in a system
a control constitut
a consist of content in a plural of intern buffer

the bu request
thi implement
the respect bu arbit
the next immedi clock cycl
the next bu master
the maximum system clock frequenc
the last port driver
the current bu master
the critic time path
the bu master
the arbitr system
the arbitr protocol
the arbitr process
the arbitr latenc
the arbitr clock cycl
technologi
system clock cycl while the latenc
overal system clock latenc
each arbitr task
bu request line in a first clock cycl
bu master
bu content
bu arbitr system
bu arbit
ani system
ani chang
an inact system
an arbitr clock cycl
a system clock cycl
a second clock cycl
a last port driver
a current bu master
a common system
a bu request in a clock cycl

a bu coordin
thi bu grant signal track the bu request
the reassert of the bu request
the node time
the node deassert the bu request
the node control of the bu
the extra cycl
the extra clock cycl of the bu grant
the deassert
the bu request signal remain
the bu grant signal chang
the bu grant
the bu coordin
set of inform
no state chang
inform signal
increas the effici of the system
extra cycl
deassert
control of the bu
consecut bu request
clock cycl after the bu request
bu grant
both request control of the bu from the bu coordin
a single bu request

a bu cycl
the subsystem processor from the second signal protocol
the second signal protocol
the first signal protocol
protocol convers between a processor
arbit signal
accord with the first signal protocol
accord with a first signal protocol
a subsystem
a second signal protocol
a method of oper in a comput system
a high perform system

a bu cycl of interest
time posit
the kernel
other featur
microprocessor base electron system
memori emul techniqu
memori emul method
line of rom
fine resolut sync puls
fault locat
fault isol
encod test result
complet function test
bu test
a target microprocessor

a bu fraction
the unit of the microprocessor
the stop clock function
the stop clock
the pipe line
the i/o clock
the condit that the bu fraction regist
the amount of time
signal line
second state
pll from bu fraction regist
i/o clock
bu unit
bu fraction regist
bu cycl in the pipelin
an i/o clock
a stop clock signal i
a stop clock function
a special cycl
a second frequenc
a number of unit
a number of nop
a nop micro instruct
a fraction of the first frequenc
a bu fraction regist

a bu id match
the system buse
the rise of a clock
the respect system buse
the number of id valu
the bu id signal i
the bu id match
respect bu interfac that transfer data at the same time
own id valu
each bu interfac
coincid of the bu id valu
associ with multipl processor
a plural of system buse
a packet signal

a bu interfac control
edg interfac circuit

a bu line
the slot
the selector output
selector for real time video signal process
lower slot in synchron with the clock
adjac slot
a plural of slot in a backplan

a bu master
three state bu driver
the type of host processor the coprocessor
the same code
the microprocessor permit specif of portion of the intern regist a sourc
the driver
the adapt
specif of the size of an alu oper
some pipelin stall
read instruct
i/o instruct
either host processor
easi oper on data
data from a regist
certain output pin
byte through 24-bit pointer
an ordinari move instruct
an intel/motorola pin
a special move instruct
a signal on a line
a separ i/o instruct pipelin
a master slave pin
a bu slave

a bu of approxim half the width of the precis
the storag of intermedi result
temporari regist
success half bu width oper
polynomi expans
mathemat function
high accuraci reduct of polynomi
full bu width accuraci
argument reduct
a partial remaind oper
a numer process system

the second processor
a first processor

a bu read invalid oper
thi second cach line
the second cach line
the invalid request
the exclus state
race condit in mesi base multiprocessor system with privat cach
race condit
bu write invalid oper
a second cach line
a plural of processor with intern cach
a particular cach line

the ipu
an instruct prefetch unit

a bu transfer request
the single cach line
the primari cach
the prefetch miss
the cach control load the primari cach with the cach line
the bu transfer
subsequ prefetch from the integ unit
issue prefetch request
integ unit
entri in a primari cach
conjunct with the prefetch request
cach load
cach line from an extern memori
a steadi stream of instruct
a prefetch miss
a cach control on a cach half line basi
a cach address memori manag unit

a bu with a larg bit number
the simultan concentr of a larg amount of inform
the parallel process oper
the multipl port regist
the gener regist
respect process pipelin
plural process pipelin
parallel process devic
a parallel process devic
a parallel instruct devic
a multipl port regist

a bu with high level statement
the major of the applic element
the asp
the applic element
sequenc the invoc of each applic element
pre design reconfigur applic element
pre design applic element
post synthesi tailor
period of invoc
each other via a bu
asp
applic specif processor architectur
applic element
an instruct program
a power manag design

a bubble
a bubble i

a budget
word growth
variou estim attribut
throughput the compil
the specif of function
the specif of accuraci
the size of the processor
the signal attribut of bit
the optim word structur for the applic
the effect of design chang without recours
subword
quantis nois
comput grain
an icon network
a word structur
a specif exampl of design
a direct relationship
a compil for a digit signal processor

a buffer for entri into the pipelin
the statu
the data from a plural of parallel process unit
the concentr of the invent
the concentr element
the capabl of the invent
repetit
these instruct without interrupt sinc particular situat
the second action
the process of instruct in data
the first i the execut
the content of the oper regist
such repetit
such event
execut phase
devic in the instruct unit of a pipelin processor for instruct interrupt
a situat
a short interrupt
a repetit of the instruct
redirect of the pipelin
pipelin diagnost
new
graphic pipelin access
further diagnost capabl
direct user access
differ data sourc
data stream concentr
data insert into the pipelin
command/data packet from a plural of parallel process unit
a user of the graphic

a buffer for input data
the same silicon chip
the plural of processor element
the number of the data bit in a seri of serial data
the multiport memori
the group of processor element
suffici arithmet oper perform
logic unit on the bit line of a multiport memori
high rate signal in real time
high program perform
a single control
a group of processor element
a digit signal processor with a high process

a buffer for instruct
variou machin resourc
unit of a digit comput
these buffer
the independ instruct stream
method for serial instruct
independ instruct stream
capabl of the comput
a select

the buffer memori
the control charact
multipl line of data
line printer adapt
dynam scan algorithm for a buffer printer
control charact from a central processor memori
a print scan cycl
a hardwar algorithm

a buffer memori a part of the devic processor
the devic processor by a dma transfer path in the devic processor
the devic processor
the common bu
the buffer memori in the devic processor
single data
multiprocessor data server
more devic processor
more commun processor
i/o control
global direct access
data transfer among the microprocessor
data server
data between the network
comput network
block of remot file
architectur of the devic processor of the present invent
a plural of secondari storag devic

a buffer rotat control circuit
the rotat of the buffer between the cpu
random buffer access for the encoder/decod circuitri
odd
linear buffer access for the cpu
error correct oper
encoder/decod circuitri
data bu control signal
an optic disk
an error control chip of an optic disk storag
an adop address
an adex address
address gener for error control system
a pipelin error control arrang

particular applic
time instruct
heurist instruct
cost base heurist instruct

interfac circuit
a vl

a buffer section
those bu line
the data selector
the buffer section
multipl bu line
deviat
adjust
the use of combin logic circuitri
the sram in an l2 cach
the natur of cmo circuitri
the l2 cach clock
the l2 cach
the amount of power
skew adjust for the l2 cach clock
seamless shutdown
rel time between clock signal
l2 cach
l2
dynam control of clock in a multipl clock processor
control clock
clock for a processor
an l2 cach
address strobe
a number of signal
a clock control circuitri
a data selector

a buffer storag control system
the tag portion
the same partit
the read access
the data portion
the buffer storag control system
tag portion
oper in the same machin cycl
everi partit
data block of buffer storag
an address for a read access
access partit of tag
access for everi partit
a two level hierarch structur
a plural of partit
a plural of address

the store address
use by an instruct execut unit
thi task
the load/stor unit align thi data
the load data
the data cach unit return 8 byte
pending
order cach
no address collis
main task of the load store unit
main purpos
load request
load and/or store oper in a superscalar microprocessor
i/o in a superscalar risc architectur environ
an older instruct
an address collis
align of data
a store oper
a load oper
a load store unit

a buffer storag system for a pipelin processor
thi feedback
the store address/data regist
the buffer storag
store data regist
store address regist
coincid in data among the storag
buffer storag system
buffer storag
an operand store oper
an operand store data
an operand store address
an operand access buffer storag
a store through method between the buffer storag

a logic address
the extra bit
bit address
an operand access control regist
a millicod instruct load a millicod address extens regist

a buffer store request
the store address data
the storag data
the second cach control circuit
the readout request
the cach buffer circuit
the buffer store request
the buffer circuit
store address data a buffer output data
store address data
storag request from the central processor
storag data
second coincid circuit
second cach control circuit
readout address data
pair of buffer
instruct cach memori
each pair
each address data into a physic address
cash memori arrang
buffer output address data
ani readout request
an address convert
a cash buffer in combin with a pair of cach memori
a cach memori arrang
a cach buffer circuit

a bug
the sequenc of processor instruct
the sequenc of machin instruct
the discoveri of processor bug
that site by virtue of the local state
that machin instruct
site on a network
reinforc
new gener network
network path
machin instruct gener for design verif
machin instruct
genet oper
ani discrep in the result
an adjac site
a site on the network
a sequenc of processor test instruct
a machin instruct gener
a logic design of the processor
a local state
a function model of the processor
a diagnost file

a built in cach memori
the number of abort
the moment
the main storag 28
the fb regist
that cach memori
high speed process
high process perform in mani field of applic
extern storag
data processor with cach memori
an fb regist
a cach memori of direct map system
a built in ram in order

a second storag devic
a first storag devic

a built in intern self test control
the test pattern gener
the memori verif element
the data from the first storag devic
commun a plural of test pattern
an error free manner
a test pattern gener portion
a single test control
a memori verif element

a bulk memori
the raster type monitor
the pixel mover
the oper of the pixel mover
the imag in the bit
the formatt
the entir imag
the display gener
the acoust control
sensor format into a varieti of display format
rapid updat
pixel address gener
parallel process of the data in parallel
own control
multipl pixel at a time
multipl block of pixel
manipul capabl
data from the bulk memori
convert acoust data
control algorithm processor
area of the imag
an independ processor
an acoust control
acoust sensor data
acoust display gener
a raster type monitor
a pixel mover
a pixel formatt
a pixel build algorithm processor
a display gener

a burst address
the first cycl
the burst cycl
the burst address
output success data element of the burst
output data from the asynchron memori core
consecut cycl of the period clock
burst memori
an input of an asynchron memori core
a third cycl of the period clock
a second cycl of the period clock
a first cycl of a period clock

a burst address gener
the synchron burst sram devic
the sram devic
the sram core
the dual task
the boolean function of the chip
the address regist
synchron sram
sens amplifi
propag of the core
oper of the synchron burst sram devic
an sram core
address for the memori array in the sram
addit address
accord with a boolean function of the chip
a synchron burst sram devic

a burst oper
the intern address of the cach memori
the cach memori control
the cach memori befor the second address
the address strobe from the processor
cach corrupt
burst oper

a first address
a second address

a burst read oper in the asynchron nonvolatil memori
the same page
the plural of individu compon
the output of a memori compon
the n lower order bit of the current address
the n lower order bit
the m higher order bit
the individu memori compon
the first address a a current address
the current address
the consecut subsequ address
the consecut address
m higher order bit of the current address
individu memori compon
consecut subsequ address
burst read oper in an asynchron nonvolatil memori
an asynchron nonvolatil memori
accord with n lower bit of the current address
a same page
a same memori compon
a plural of individu memori compon
a current page
a consecut subsequ address
a burst read oper refer consecut address

a busi next adjac further node
the present time
the node for a link
the function of path
the function of data
redund test of path
no next adjac further node
further test
failur
exhaust test of all path
data transmiss mode
connect analysi
aspect
the illumin color
wide apertur
transit color
third illumin color
the sheet in a movement direct
the scanner
the scan direct
the pixel area with the illumin color
the photodetector array
the color of the light
the coher fiber optic i
small apertur
sequenc of pixel color signal
light onto a seri of pixel area of the sheet
intens
illumin
each pixel area with the same signal
each pixel area
area of the sheet
area move across the sheet in the first direct
an intens
an illumin color signal i
adjac pixel area
a sheet
a scan direct
a pixel color
a photodetector array
a first direct across the sheet
a composit color for the pixel area
a coher fiber optic bundle
a chart
the illumin
an intermedi node
an intellig channel
adapt
the fft
small target sensit
function on a rang gate basi
clutter in that rang gate
clutter cancel
an adapt weight circuit
agc circuit
a radar signal processor
a separ path setup mode
a next adjac previou node
a multi node network
a minimum cycl breakdown of the possibl path
a list of node
a destin node

a busi signal
the other pipelin
the fpu pipelin
the first stage of the fpu pipelin
point unit pipelin
pipelin caus stall
both pipelin
an fpu pipelin
a first execut stage of the fpu pipelin

a master processor
the variou modul
the processor within the modul
the host unit by a unidirect token ring
processor design
flow of data
multipl processor acceler for logic simul

a busy/readi
the valu of a busi regist
the slave processor output
the slave processor in a slave access cycl
the master processor activ the slave processor
the master processor
seri product
intervent of the master processor
gener purpos product
exampl a vector oper
a vector oper under control of a master processor
a vector length for a vector oper

a bypass address
the destin address within each execut unit
the bypass
system in a specul execut microprocessor
everi potenti sourc operand
a specul execut microprocessor

a bypass circuit
the bypass circuit
multi stage data processor
an operand bypass mechan
an ident locat in the memori
a control devic with respect

a result buffer
the same number of slot a the result buffer
the result for that instruct
the condit code buffer
slot in the result buffer
precis architectur state of the processor
out of order result
out of order condit code
instruct in the processor
each specul result
each slot in the condit code buffer in one to one correspond with a slot in the result buffer
ani condit code
an architectur result regist
an architectur condit code regist
a slot in the result buffer
a number of slot
a condit code buffer

a bypass control circuit
the plural of entri
result of the instruct
result of an instruct
result buffer
a sourc address of data
a plural of address of a regist file
a destin address

instruct in respons
the occurr of a branch instruct in the pipelin regist
the next clk
the micro instruct gener
the load of a new non sequenti instruct address
system of macro instruct regist
special branch instruct
sequenti oper
rate while the pipelin regist
micro instruct gener
clk 2
clk
two level prioriti circuit
both macro
a variabl clk 2
a two tier synchron arbitr system for memori request
a constant clk
prioriti circuit
high speed synchron comput

a bypass help instruct
the sourc operand of the miss instruct
the same element
the miss instruct
the miss address
the input address
the help instruct
the fill help instruct
the fill data
the fill address
the destin of the miss instruct
the bypass help instruct
the appropri row of the data cach
pipelin of the microprocessor in a fashion
cach access address
a second pipelin stage
a fill help instruct
a data cach miss

a bypass mechan
the result buse
the read stage of a subsequ instruct
the latter instruct
read port of the regist file
operand read
operand for variou oper
multipl instruct pipelin
gener of a product from the multipl oper
execut result of the oper
each regist of the regist file
data path circuitri for processor
an instruct datapath circuit of the processor
a plural of result buse
a multipl oper
a latter instruct in the pipelin

a bypass multiplexor bypass the execut result
the storag unit store instruct
the schedul dispatch for execut a data depend instruct
the out of order execut processor
the indic of futur avail of the hardwar resourc
the execut unit for execut
the execut result of the sourc instruct
the data depend instruct
the bypass multiplexor
such sourc instruct for an operand
futur complet of execut of sourc instruct a number of clock cycl befor actual complet of execut
futur avail of resourc
futur avail of hardwar resourc
dispatch that instruct
data depend instruct
back port a number of clock cycl befor actual avail of the hardwar resourc
avail of resourc
an out of order execut processor
a storag unit

a bypass path
these error correct decod calcul
these calcul
the trigger circuit
the time of the trigger
the r q degree calcul
the number of gener cell
the natur of the error correct polynomi
the input of the calcul
the error locat polynomi calcul
the delay path
the bypass path
the appropri calcul
subsequ cell with the time of calcul
reed solomon error correct calcul
reed solomon circuit for differ reed solomon code
r q degree calcul
memori element and/or delay element
appropri calcul
an r q degree calcul
an r q calcul
an invers error
an error locat polynomi calcul
an error correct decod
an adapt delay
adapt circuit that use switche
a trigger circuit
a standard error locat polynomi calcul
a plural of gener cell
a multiplexor
a delay path

a bypath
the data on the bypath
data among pipelin
bypath
an integ oper unit
a vliw microprocessor

a byte basi
unit for execut
the pipelin between the instruct
the orthogon instruct
the configur of the pipelin in the orthogon instruct
pipelin in the instruct
orthogon instruct
oper in the orthogon instruct
non orthogon instruct
kind of pipelin
each part of a machin word
each operand
accord with common pipelin control
a pipelin between instruct

the result of the arithmet oper
the arithmet oper unit

second operand
the second arithmet unit for normal
the second arithmet unit a second time
the first arithmet oper unit
neg expon
each arithmet oper unit
a second arithmet oper unit
a result of the arithmet oper
a normal
a first arithmet oper unit
a denorm

a byte from the operand buffer
the translat instruct
the overhead
the address calcul
the address adder the data
temporari store
oper by use of a plural of address adder
everi n second operand
each operand of an instruct
depend operand
an oper procedur
address calcul adder
a byte of the first operand

a byte in regist
the rightmost hexadecim digit
the hexadecim digit from a plural of byte
store hexadecim digit
step in millicod regist
plural of byte
millicod regist r2
millicod instruct for certain decim oper
extract step
each hexadecim digit
a millicod method
a byte in regist r2

the updat
thi target address
the last occurr of each branch instruct
the instruct in a branch predict cach
the branch predict cach from the system
the address of instruct
the address of an instruct
that entri in the instruct cach
such instruct
normal execut of instruct
entri in the branch predict cach
branch predict cach consist
attempt
store-into instruct stream detect
an instruct pipelin from the cach
an instruct in the branch predict cach
a subsequ attempt
a separ instruct cach
a record of the target address
a copi of the first sever instruct
method an apparatu for store-into instruct stream detect

a c limit check adder
superscalar execut unit for sequenti instruct pointer updat
segment limit check within a cycl
segment limit check
next eip
multipl sequenti instruct pointer updat
embodi of the execut unit
current eip select
combin logic
an eip histori ram
a limit fault histori ram
a dual eip adder

a cach access
the second power down circuit
the first power down circuit
the control signal disabl a clock
signal disabl a clock
second power down circuit
power down scheme for idl processor compon
power down circuitri in a processor
instruct a input
function unit of the processor
a predict circuit

a cach access circuit
the content of the cach
reset by a user
an invalid bit

a cach access system that shorten the address gener machin cycl of a digit comput
the virtual address into a real address
the synonym problem
the real address
the last real address
the histori of instruct
the gener of the logic address
the concept
the cach memori for a particular instruct
the address gener machin cycl
the adder of the virtual address gener
incorrect guess

a cach block from the instruct cach
the search address
the particular start
the packet unit concaten data word of an instruct sequenc into contigu block
the packet unit
the next cach block
packet unit
multipl set in the tag ram
multipl cach block
mechan for variabl length instruct
final data word of an instruct sequenc
final data word
cach block
associ fashion
adjac locat of the queue
a tag ram
a search address for output
a search address

a cach coher
up to date copi of that line
the rang into a second section of the operand cach storag section
the near futur
the instruct categori with each instruct
the instruct cach a a result of context switche
the first section
regard a single i/o cach a an exclus buffer
onli instruct of the categori
map physic address
i/o cach
everi access
coher cach structur
cach coher statu bit in a global memori
ani refer
an operand cach
an associ directori
all stack frame of user program
a page map i/o cach structur interfac by a larg number of i/o channel
a line of data
a group of statu bit
a first directori
a cach coher techniqu

these element
the tap counter
the serial data
the serial clock
the serial access regist
the next posit for serial access
the i/o
the end of the serial clock cycl
system design
serial input
serial data into a pipelin
serial data
serial connect an input latch
no increment
neg setup time
multiport memori
equilibr of digit line
convers regist into memori
a video random access memori
a time befor the parallel transfer of data
a tap counter
a serial input port
a serial clock
a second isol gate
a multiport memori
a first isol gate

memori address
a memori address

a cach coher mechan
the privat cach
the overal perform of the multiprocessor comput system
the cach coher mechan
success cach coher basi transfer
privat cach
multipl of the basi
minimum complimentari cach coher action
an i/o devic
all data transfer
a memori data

a cach control for a system
the statu inform of the first level cach
the number of sram
the multipl stage
the l2 cach tag address
the first level cach for current read oper
tag address
second level cach memori
multipl stage address
multipl physic cach
multipl line replac of the first level cach memori
multipl bank
modif in the l2 cach
local read write storag for use by the processor
current first level cach
certain statu inform for the second level
bank of the l2 data ram
a number of l2 cach line
a next address in the first level cach
a miss in the first level cach
a look up system

a cach control logic circuit
the tag unit
the statu inform
statu inform for both tag cach
simultan cach access
data tag cach
collis
address locat in a data memori
a tag unit
a statu bit array
a multi process system
a data tag cach
a collis

a cach control unit
the second cach request
the first cach request
second cach request
cach control unit with a cach request transact orient protocol
a second cach request
a request identif inform
a first cach request

a cach control with a comput readabl cach memori
the textur map engin
the textur engin stall
the tda circuit
the 3d graphic
textur map data
textur map address
textur data request
onli n cach miss oper
fifo memori unit
effici of textur map data request within a 3d subunit of a comput
a textur map engin
a textur map data access
a textur map address
a polygon engin
a pixel pipelin

a cach data
the store mechan
the same pipelin stage a the cach access stage of a subsequ instruct
the cach tag read of a subsequ store instruct
return from memori
pipelin store instruct
load instruct of the present invent
effici pipelin format for each instruct
an immedi determin
a uniform number of cach access stage
a single cach access stage
a single cach access pipestag
a free period of the cach
a cach read

a cach data unit
the pipelin into the cach
the pipelin after the store
the ownership
the continu flow
the cach data unit
store output from the pipelin into a store in cach
store into the pipelin
processor ownership
insur data integr in process ownership indic
data for a store in cach
ani processor ownership chang
an ownership interlock on the data unit in a pipelin
an ownership interlock
an ownership chang
a store in type of cach
a data unit in the cach
a continu flow of store
a chang of processor ownership
a chang of ownership

a cach line from the fill buffer into the data cach bank
the write back buffer
the fill buffer store
the data cach bank
the cach line of data cach unit of each other microprocessor
out of order process of memori instruct
more cach line for transfer into data cach bank of the data cach unit
each microprocessor
a victim cach line from the data cach bank into the write back buffer
a single clock cycl line replac in a data cach unit
a single cach line
a separ write back buffer
a separ fill buffer
a particular implement
a non block cach

a cach memori control
time with the servic
the servic
burst read

a cach memori for branch histori inform
the target address from cach
target address in addit
inform in the cach
inform from the cach
displac match
displac for the branch
branch bia for the branch instruct
a predict bit
a length

the memori refer instruct
the instruct schedul
the actual memori locat
regist operand field
pattern of past histori
operand field of a set of instruct
memori refer instruct
issuanc of the instruct
an instruct schedul
an instruct box
a regist mapper
a more like predict direct of the branch instruct
a memori refer

a cach memori from main memori
virtual prefetch
the virtual prefetch instruct
the redund prefetch instruct
the prefetch instruct with virtual prefetch instruct
the prefetch instruct
the origin prefetch instruct
the kernel section
more actual prefetch
execut of other instruct
depend relationship between the prefetch instruct
a plural of prefetch instruct
a kernel section of the schedul
a depend graph

a cach memori subsystem
the total avail cach memori space by separ account replac
the presenc of a multipl alloc
the mam
the lower prioriti
the buffer memori stage
space of the other process unit
processor storag locat
multiprocessor coher cach system
multilevel directori memori
independ oper
entri replac
earliest data replac
each directori alloc cycl
buffer memori pipelin stage
a multipl alloc memori

a cach memori within the pipelin
the provis of a cach memori within the pipelin
the oper of the pipelin
support
oper for the comput processor
data from the regist
an integr cach
a load/stor pipelin in a comput processor

a cach mode
transpar translat regist encod the serial
the request of the function unit in accord with the issuanc order of the request by the function unit
the page descriptor
the issuanc order of the request
the function unit issue request
the access control
memori access serial a an mmu page
memori access in the instruct sequenc
an access control postpon
an access control
all appropri except
a set of page descriptor
a serial
a page basi

a cach start
the independ instruct
the cpi
the branch instruct in the memori
store valid instruct in an instruct memori
put the independ instruct behind the branch instruct in the memori
perform of a microprocessor
an order control

a cach storag devic
vertex data
the redund matrix transform
the perform of a comput system
the graphic imag
polygon form
out the window simul
control hardwar
conjunct with a pipelin graphic
comput graphic vertex index cach system for polygon

a cach storag system
system for execut
storag storag instruct within cach buffer storag
storag immedi instruct
hardwar for in cach execut
a separ execut unit

oper code field
the tag field of the instruct
the memori by way of a cach storag unit
the comput instruct
more comput instruct
instruct issue time
each instruct a tag field
inform block
differ one of the function unit in accord with the coding
a plural of function instruct
a main memori unit

a cach storag unit
these function unit
the higher level storag unit
the cach unit
the cach storag unit
process the instruct
machin level comput instruct
journey from a higher level storag unit of the comput system
instruct in the instruct stream

a cach subsystem arrang for effici manag of input/output oper
the non cacheabl data block
the non cacheabl data befor storag
the cach arrang
system sinc multipl processor
serial store oper
processor in a multiprocessor system
non cacheabl data
more store
higher perform in the multiprocessor system
fewer bu transact
cach arrang
buffer queue for non cacheabl data
buffer into non cacheabl data block
bu transact bandwidth
an input/output devic
a system bu i
a network devic
a display devic for exampl

a cach system
the slave of these bandwidth rob duti
the master cach
smaller slave cach
the complex cach manag oper for the slave cach
a larg master cach
slave cach

a cach word
the processor further halt the processor pipelin
the processor befor a valid determin
the extern cach memori
the cach word proceed
the cach word a an instruct
obtain
instruct from the extern cach memori
execut by the processor
an extern cach memori
a microprocessor system
a late cancel method
a high perform microprocessor system

a cad system
the stage at those point
the cad system
stage in a comput aid design system
signal process time for divis of the stage
signal process time
new netlist for the new stage
circuit locat

a calcul result judgement section 7 judg
the load instruct by a pipelin
section 3 in advanc
regist inform
load address predict method
load address
instruct into a load instruct inform
data hazard
data a the execut result of the load instruct
an address calcul section 3
a load instruct inform registr section
a load address

third object posit
third fiduci posit
the motion refer frame of a moveabl object
the fiduci move
refer frame of the camera a a function
refer frame of an imag acquisit devic
posit of the object in the motion refer frame
posit in the motion refer frame
pixel width
pixel height of a field of view
an orient
a third fiduci posit in the field of view
a second fiduci posit in the field of view
a motion
a first fiduci posit in the field of view
a calibr relationship between the motion refer frame of the object
a calibr relationship

a calibr relationship between a camera
those locations/orient
those imag
the refer frame of the camera
the motion refer frame of the object
the locations/orient of the target
the location/orient of the target with respect
the camera refer frame a a function of the locations/orient of the object with respect
the calibr relationship between the refer frame of motion of the object
plural locat
nonfeedback base machin vision method
imag with respect
imag of the object
an imag of the object
a refer frame of a camera
a moveabl object
a calibr relationship between a refer frame of motion of an object

a call
unit with a return stack
the target cach in addit
the return stack pointer
the return stack control logic
the return stack control
the resolut pointer
the confirm pointer
return stack pointer repair in the case of the failur of a call/return
return stack control logic
repair
pointer from differ pipe stage
call/return pair
addit stack pointer
a return stack pointer
a return stack for call/return
a resolut pointer
a confirm pointer
a call/return pair

a return address
the second stage verifi predict
the return stack buffer
the return address in the return regist
subroutin instruct
return from subroutin instruct within the instruct stream
return from subroutin instruct in order
return from subroutin instruct in a comput processor
return address for return from subroutin instruct
perman state
each time the second stage decod a return from subroutin instruct
each time the second stage decod a call subroutin instruct
apparatu resolv return from subroutin instruct
a stack of return address
a second stage decod each call subroutin
a return stack buffer
a return from subroutin instruct
a return address in a return regist
a fourth stage
a call subroutin instruct

a call predict
the return predict
the program counter regist
the predict cach memori store interpret call predict
the predict cach memori
the microinstruct of the interpret
the instruct cach memori store instruct of a program
the entri address of the instruct interpret
the call predict
normal program flow
multicycl instruct
microinstruct of a multicycl instruct interpret
interpret entri address at the address of the multicycl intruct
branch instruct predict
both single cycl instruct
an instruct cach memori
a return predict
a program counter regist
a predict cach memori

a cam
the earli read oper of the address of the destin regist of the reserv station while the remaind of the reserv station
the earli read logic i
the dispatch stage
the address of sourc regist of other instruct
the abov function for instruct
maximum throughput effici
immedi schedul of instruct
entri of the reserv station
data depend inform in time
back to back schedul of instruct
an earli read oper of data
an address of a destin regist
a non clock read memori
a clock read implement

an output regist
an input regist
the input regist

a cam core
the memori associ function
the cumul result
the cascad
the cam core
parallel composit data
each cascad
content address memori cam system
cascad content address memori
cascad
cam core
a system for a pipelin
a separ data input

a cancel circuit
the object branch instruct on the basi of the output from the regist
the highest prioriti of branch instruct
prefetch an instruct
object branch
execut of instruct after a branch instruct
branch judgment result in pipelin

an address for an access
a variabl number of stage in a pipelin
a pipelin process
a memori access of operand data for an extern memori

a cancel type except
the execut of a delay slot instruct
the delay slot instruct
either oper
branch execut function
anoth processor apparatu split
an except process handler
a complet type except

a candid defect
the circuit pattern
the candid defect
the basi of the local imag signal read
electr conduct
each local imag
defect in circuit pattern
candid defect
a region
a refer circuit pattern imag
a part of the imag
a local imag
a circuit pattern

a candid instruct
the prior art list
the non squeez instruct in the initi minimum schedul
the non squeez instruct
the code gener of a compil
that factor
techniqu with a number of improv
size calcul
schedul of basic block of a program
schedul factor
non squeez instruct distinct
non squeez instruct
instruct for execut on a multi issue architectur comput
increas parallel in program loop
differenti of instruct
a multi issue architectur comput

full adder
a new carri bit

a carri bit from a lower order bit comput
systol array for matrix matrix multipl
row element
product matrix element
mutual counterpropag therethrough with a cumul time delay between input of adjac column
later addit
input data bit
individu cell
either side of the array
column element
bit level matrix interact for product matrix comput
bit level contribut
an input cumul sum bit
a systol array of nearest neighbor
a higher order bit comput
a digit data processor for matrix/matrix multipl

a carri input
these n product
the summat input of the adder
summat of all partial product
row by row
respect delay unit with a sum input
product sum
n product from pair of multidigit binari number amn
each basic cell
connect for the b coeffici input
bkn
an overal array
a summat input
a logic gate
a half clock
a delay unit for the a coeffici input

a carri save add circuit
the set of carri
the same memori address locat
the carri save add circuit
subsequ clock cycl
multipl independ processor
instruct in consecut clock cycl
feedforward
the sign latch microinstruct control
the pipelin controlsequenc
static ram and/or
programm horizont format microinstruct
point vector processor
point format multipli
pipelin input
pipelin control sequenc
output data depend address gener
logic unit with a data depend decison
intens function
feedback data
dynam ram
dma i/o
configur multifunct
address gener for data
address fifo
a wide bandwidth data memori
a user select plural
a sign latch
a read address fifo
a microinstruct
comput system architectur
a set of carri

a carri save addit
the adder complex
effect manipul of 2
better time
area/tim effici motion estim micro core
area perform
an effici micro architectur for motion estim
accumul oper
absolut

a carri stage
the sourc of the pmo transistor
the sourc of the nmo transistor
the output sum
the output of the invert
the gate of the pmo transistor
the gate of the nmo transistor
the drain of the pmo transistor
the drain of the nmo transistor
signal with respect
reduct of partial product by applic of a booth mcsorley process
partial product
partial output sum signal
one bit adder
diagon propag of cari
complementari analog cmo switche
cmo complementari pass transistor
applic of a carri
an nmo transistor
an invert
all sum
adder in intermedi row
a pmo
a one bit adder
a fast multipli

a cartesian
the result valu of q
the q
the precis growth
the orthogon axe
the number of rotat
the next rotat
the msb
the magnitud of the vector
the increas
the cordic magnitud circuit
small magnitud vector
rotat after the first rotat
q word
q compon
portion of the magnitud circuit
polar coordin convert
phase of a complex number
orthogon compon
one half
make room
lsb
jq
higher precis
cordic magnitud circuit
cordic
complementari metal oxid semiconductor
cartesian coordin by the complex number
bit posit at each rotat
angle of a vector
an iter process
advantag of the fact that each valu of q
addit bit of precis
accuraci increas in direct proport
a typic cordic magnitud circuit
a larger word size
a cordic magnitud circuit

a cascad
the processor of the cascad
the first bau in the cascad for subsequ pass
tempor offset
multipl stage fft signal
manner store four stage partial fft
each bau in the cascad
each bau
a pipelin fast fourier transform arrang

that stage
the token a control token
the single two wire interfac
such stage
subsystem circuitri
data in token format
control token along the pipelin
control token
both control
a wide varieti
a two wire interfac

a cascad of a plural of transform stage
the subsequ stage
the propag of the control signal
the other line
the next stage along the cascad
the imag data the integr of the data
pipelin imag processor
imag data through the cascad
each signal i
data from the previou stage
control line coupl each pair of adjac stage
an orderli manner through a long cascad of stage
an imag morpholog process system
an idempot transform
a pair of handshak data

a case of the wire in a zigzag fashion
the wire
the outlin of the peripheri
the outlin
the longitudin side along a line
the entir length
side of the metal
non metal sheet
later distanc
joint of steel pipe in oil pipelin
cabl
a zigzag fashion

a castout stage
thi address calcul stage
the invalid directori entri in the array of directori entri
the flush signal
the directori entri modif stage within the high level cach
the directori entri modif stage invalid the directori entri
the directori entri modif stage first look
the directori entri lookup stage
the directori entri from the directori entri lookup stage
the castout stage
the array of directori entri
the address of a directori entri
retriev the directori entri
no further process
invalid of lower level cach
content of the high level cach
an array of directori entri everi clock cycl
an address from the address calcul stage
a new oper everi clock cycl
a line in the low level cach
a l2
a invalid directori entri
a high level cach
a directori entri modif stage
a directori entri lookup stage
a directori entri from the directori entri lookup stage

use connect pattern
the interconnect pattern
repres configur
pyramid
the pyramid learn architectur neurocomput
the pyramid base
pyramid arrang of processor array
level in plan
architectur neurocomput
programm choic of network configur
process data
polymorph mesh network imag
polymorph mesh
physic mesh connect
mesh of network interconnect
mesh of interconnect
configur the network
an imag procssor of cellular automata under softwar control

a ccd
the shift regist array
the analog shift regist
the analog output
the addit of input signal
signal processing for a plural of signal
signal processing
shift regist mesh
sequenc in time of control for shift direct
mesh
arithmet addit
analog shift regist
a systol array processor
a shift regist array
a plural of signal processor
a plural of shift regist
a parallel manner on an analog type shift regist array
a number of analog type

a ccd array
the optic fiber
the light through a window
the light from the light sourc
the field of view in the focal plane
process reactor vessel
pipelin at full process concentr
particl
optic
high peak power output
droplet
an optic fiber
an in situ imag system
an imag of a multi phase fluid
an imag detector
a probe
a light sourc
a len system near the end of the probe

a ccd sensor
the second interv of the video
the imag pixel
the first interv
the digit black clamp circuit
the d/a convert
the black level of an imag
the a/d
second input of the differenti amplifi
no advanc knowledg of dark mean level
digit process
digit black level
ccd dark mean level correct circuit
analog subtract
an averag black level
an a/d convert
a sourc of a video
a second interv of imag
a first interv of black level pixel
a digit black clamp circuit

a cell
virtue of thi accumul
the tree
opposit side of the array
nearest neighbor
later comput of a contribut
input in counterflow
individu output term
data element by coeffici
data by a coeffici
cell redund
an earlier comput
an adder tree
adjac cell
addit in a subsequ comput
a systol array of cell
a cumul sum bit from a cell

a cell bodi
vci
the vci
the reassembl
the major subsect
the cell bodi
the ccitt
the cam
mid for connectionless
mid
list manag
list data
each cell bodi from that cell bodi
data into a plural of atm cell
cryptograph support in a network
class 4 connectionless transfer atm adapt layer
an atm cell process pipelin
a virtual channel identifi
a segment
a reassembl
a plural of asynchron transfer mode
a lookup control
a host interfac
a decrypt devic
a cell manag

a plural of cell
the highest repetit frequenc
the full array
the cell of data bit
smaller number
smaller array
repetit of the clock
part in a maximum
larger number
cell oper
cell array
a regular array of ident process cell
a logic oper
a cell oper under the control of clock

a cell descriptor in the rate queue
the segment unit control memori store two dimension queue with first dimens rate queue
the plural of channel
the atm network
second dimens channel queue for each channel
processor for asynchron transfer mode
logic control
descriptor for cell of differ channel
control memori
concurr multi channel segment
cell in an asynchron transfer mode
a plural of channel for transmiss
a commun unit

a cell in a memori array
data path in a memori devic
data from a memori devic
a single conduct path coupl the data
a dc sens amplifi
a data output circuit in the memori devic

a cellular array processor
vector in the comparison phase
the util of common hardwar for all phase
the recognit process
the exchang of data
the end of a word
the capac of all processor
sever success phase
gradual transit between end
filter in the featur extract phase
featur extract
element of equal length
comparison with refer word
beginning of word
avoid of idl time
an exchang between adjac processor
all refer word in a speech recognit

a cellular logic oper processor
the transform valu
the state of the data
the digit storag devic
the data point of a first matrix
output by the processor a the transform valu of the central data point
number of data point of a second matrix
neighborhood
the output inform from each row
thi new analog data
the oper on that portion
the oldest inform
the new slice
the neighborhood oper
the inform from the transduc of the oldest row
the content of the latch stage
the analog data
the analog buffer
oper on an n dimension process plane
number of success scan
number of success row of the entir array
neighborhood oper
inform from a slice
inform from a new row
column line
co operand oper
an m by n
all repres slice of the total array
a single row of new data
a seri of output signal
a multi stage analog buffer
each tap
each neighborhood of data point from a first matrix
digit storag devic
data point in a matrix
cellular logic processor
a plural of transform valu
a plural of tap
a neighborhood of data point
a look up tabl i
a digit storag devic
a central data

a cellular process system
the special function process unit
more imag
imag data from the imag memori
function processor
digit data signal
data bu mean
cellular process system
an imag combin
a specif oper
a plural of special function
a matrix of point

a central clock circuit
the plural process section
the plural of section clock circuit
the plural of section clock
the common state
suspens
plural process section
each section clock circuit
clock signal in a synchron process system
a plural of section clock circuit

a central control
upstream cell
the transfer of data
the data group output from the latch
the cell memori
storag medium
parallel out latch
output from the latch in pre determin group
each unit cell
downstream cell
differ oper on the data
data matric
data from the first portion
anoth portion
a memori in the form of a shift regist

the system bu i
the return data from memori
the origin
the likelihood of a cach
writeback
separ queue
the bu protocol
other access
cach invalid
bu transact
arbitr for bu grant
an id field
address/data transact on the bu
a writeback cach
a pointer arrang
a hierarch cach arrang

the same control a the memori
the same buss
off chip processor regist
intern processor regist
i/o refer
full physic address

the last stage
point processor function
low order bit of the result
cycl of latenc
a trial mini round i

a central control unit
thi modif for the next instruct
the r/ pin
the normal instruct issue process
the idl state
the idl mode
remot diagnost system
pin on the chip
other microprocessor function
multi processor synchron
modif of regist
memori for a first instruct
instruct into the pipelin
direct memori access oper
diagnost
the cach data
method of cach
group of regist mask bit
error transit mode for multi processor system
ecc circuit in the cach
cal type instruct
an error transit mode
an empir algorithm
access rule
a non recover error
a minimum number of cycl
a maximum of access by the system for data block
ani oper
an instruct boundari
an idl mode of oper
an idl mode
an addit pin
acknowledg
a secondari control unit
a run/stop pin
a run/stop

a central execut pipelin unit
the word address portion of the virtual address
the format of a virtual address
the execut of instruct of a synchron central processor unit
the execut code for that unit
the execut code
the central unit
the carry
the cach unit of the cpu
the address inform of an instruct
sum of an effect address
real page number
program order from an instruct
memori command signal
execut unit control signal
data align signal
data align control signal
an instruct field
an execut code
a gener purpos digit data
a distributor of the central execut pipelin unit
a central pipelin execut unit

the record
station

a central locat
uniqu characterist
the specif pipelin
the locat of a leak in a fluid
the leak
the chang in the criteria a a function
regular interv
leak in a fluid pipelin
fluid flow criteria
extrapol
each locat either pressur
each algorithm
chang in the presenc of a leak
appropri action in respons
an output devic commun the locat of the leak
a record of fluid flow criteria

a central memori through a plural of memori refer port
vector processor with select use of vector regist a operand
use in vector
the transfer of inform
task of a single job
result regist
priorit
unit with target cach read priorit protocol
the up direct
the state of the up/dn prioriti bit
the read priorit protocol
the next cach access
the new entri for output by the cach
the entri with the lowest way number
the entri with the highest way number
the down direct
priorit for multipl hit in the set the up/dn bit
multipl hit
each new entri
dn priorit
an up/dn read priorit protocol
an up/dn prioriti bit
peripher storag devic
multipl critic code region
intra processor oper
inform between the central memori
independ task of differ job
i/o port
either processor at rate
differ one of sever differ type of memori refer
data from a function unit
address memori
a vector regist design
a pair of processor
a conflict resolut circuit

a central offic clock synchron the modem transmitt
the next cancel bank
the next cancel
the n mdsl modem
the modem pool
the correl vector
pair subscrib loop
output of all n adapt filter
n next cancel
n logic xdsl modem
n adapt filter of size m
each modem
each cancel
each adapt filter
channel next cancel for mdsl modem pool
cancel bank
a transmitt part
a revers channel near end crosstalk
a receiv part
a central offic xdsl modem pool

a central process complex
the maximum memori access rate
the control processor
sort/merge/join unit
simple oper
portion of the queri
portion of complex databas oper with function
perform on complex queri
mani differ databas function
field in a host memori system
field extractor/assembl
effici execut of the function
each function unit
control processor
all function unit
a predic evalu
a memori interfac
a hasher

a central process unit of a comput system
the stall cach
the next data access
the intern instruct
the instruct decode/fetch instruct data unit by a data
the central process unit without the delay of an extern data
instruct stream stall
an intern instruct
an instruct decode/fetch instruct data unit
an extern data
a stall cach

a central process unit with a float point multipli in parallel with an arithmet logic unit
the peripher port of the microcomput
the peripher port
the peripher bu
the on chip ram
the on chip memori
the memori element
the first time multiplex bu
the configur of the microcomput
that access
substanti flexibl
simultan program
set of data line
set of address line in time multiplex fashion
separ memori address
second memori
peripher port for access of extern memori
output function
on chip ram
on chip peripher
memori map input
memori buse
memori access via data line
input/output function
first memori bu
comput intens applic
a single memori address space
a second memori bu i
a plural of regist a multipl accumul

the collector
a result stack
a master safe store regist in program order

a central processor for a gener purpos digit data
the third cycl
the result of the execut of the instruct of the program in execut
the result of the execut of each instruct by each execut unit
the plural of execut unit
the order of issuanc of the instruct by the central pipelin unit
the fourth cycl
the first stage of the central pipelin unit
the fifth cycl
the central pipelin unit
the address prepar of an operand
the address prepar
stage obtain instruct
result of the execut of instruct into the operand cach
program in program order from the instruct stack of the instruct
instruct from the instruct cach
an operand cach for operand
an instruct cach for instruct
a differ set of instruct of the instruct repertoir of the central processor
a collector unit

a window
the system display
the scan convers process while the extern hardwar
the particular regist
the host cpu
the frame buffer
the display hardwar
the degree of pixel
system capabl
raw pixel valu into valu
processor by the host cpu
primit
pixel oper
pixel into the frame buffer in respons
other high level graphic processor
other hardwar
manipul system
manipul of pixel valu in a frame buffer
interpol oper
hardwar architectur for imag gener
execut of the command
clip
an imag gener
an illumin processor
an extern processor
a seri of self actuat regist
a particular command

a central programm control commun with the pipelin over a single commun link
valu of pixel in a matrix of point
transform control instruct
three dimension imag data
the processor portion of each stage
the processor for analysi
the pixel valu data
the memori portion
off imag detect circuitri
nonlinear boundari for the imag matrix
neighborhood transform logic circuitri for an imag analyz system
multi valu pixel valu
imag border
differ raster scan line length from variou imag sensor
binari pixel valu
a wide varieti of analys on both two dimension imag data
a serial stream of digit electr signal
a memori portion
a line storag devic

a central queue in the interchang control system
the user processor
the network subsystem
the control messag
simultan connect among user processor of processor base commun equip
packet data transmiss
packet data connect
origin
the respect current inject sourc
the refer node
the analog current sum
precis valu
multilevel bu driver
insect precis magnitud of current from multipl locat into common line
digit equival
current sourc
current level
bia
true differenti output
the differenti amplifi
the current sourc node
the current sourc
the current sink node
the complementari pair of transistor
respect output signal
respect input signal
pair of complementari mo transistor
invert
fulli differenti amplifi
each current sourc
differenti amplifi
current i
complementari pair of transistor
common mode signal reject
a respect complementari pair of transistor
a pair of pmo current sourc transistor
a pair of nmo current
a pair of current sourc
a current sourc node
a current sink node
analog sum of the net current
analog current level in each line a an aspect of convers into digit form
a typic applic the current sourc driver
a refer gener on each chip
a current sourc
node control
network via packet link
gateway
destin of data commun packet
control messag
an interchang control subsystem via variou control messag link
all control messag
a packet frame synchron
a digit switch network

a central unit
the station
the realm of an inform
the output interconnect
the input interconnect
that station
sever processor
sever memori via an input interconnect
respons from those memori via an output interconnect
memori increas
input station
feedback shift regist
back shift regist
an analog devic
a station
a ring of station
a notabl applic

a certain categori
track of the pipe
the pipe number
the oldest instruct in the pipelin processor
the multipl number of instruct stream in a multipl number of pipelin processor
the dynam histori
other characterist of the instruct
oldest instruct
leav room for insert of the particular instruct
futur refer
float point single instruct stream single data architectur
execut of the oldest instruct in such processor
each pipelin processor
dynam multipl instruct stream multipl data multipl pipelin
categori
a record of the pipelin processor number
a multipl number of pipelin processor
a multipl number of instruct stream
a dynam multipl instruct stream
a dynam histori tabl

a certain class of systol array
time in area time effici
throughput capac
the advantag through appropri choic of digit
signific benefit
processor util
origin design parallel bit processor with digit serial processor
maximum common divisor of latenc around the loop connect
high speed arithmet calcul
digit serial process
digit serial comput
digit serial arithmet i
digit serial arithmet
bit parallel arithmet into array
an exampl
an area time effici method
a well known band matrix multipl array

a certain output state
the control element output
processor statu signal
processor in the seri
pipelin method
both input
a seri by data line
a number of data processor
a number of control element

a chain
the target track
the summat pipelin
the estim of the true target track
the coordin trajectori
target track
target motion analysi
target detector
target align with the coordin trajectori of an actual target
sum of short term spectral valu
spectral valu from short term valu of frequenc
sonar processor
non acoust data
local with an algorithm
local for passiv sonar
frequenc address
each ram
data from an array
data from a passiv sonar array
data for a single two dimension fraz spectrum
beam spectra
angle coordin valu
adder in the summat pipelin
a track gener
a system for target detect
a summat pipelin
a search grid in the form of vector

a chain of command
the pipelin until the last of such fragment
the oper of the data pipelin facil
the next command in the chain
the last fragment of data
the instanc
respect leg of the pipelin
receipt of the user request
adjac command in the chain
a sourc of the data
a respect leg of the data pipelin
a request for particular data
a plural of fragment
a facil
a data pipelin in a data

an architectur
flexibl architectur

a chang in physic memori
translat of virtual memori
physic memori
optim sever higher level processor oper
notif on hardwar
memori alloc
internod messag
data movement with hardwar oper
data movement
aspect of data movement oper

a chang in the instruct flow
the flow control indic
the correct instruct flow
the chang of instruct control flow in a microprocessor
the chang in flow
that flow
instruct flow
a separ instruct in the pipelin
a flow control indic
a correct instruct flow

a chang in the potenti differ between the digit line pair
semiconductor memori devic
an uniform read delay time
a row address
a parasit resistor
a pair of digit line
a logic oper of a write/read
a load element

a channel adapt
voter
the symbol plane
the other side
the memori function
the complet process core
reliabl semiconductor data storag system
other function entiti
multipl symbol plane
memori word
least symbol plane
individu fault contain region
ident process core rail
each symbol plane
each rail
each fault contain region
each channel link adaptor
detect code bit for all data
data link
correct of all data
core rail
core modul
commun channel
client processor
an error correction/detect mechan for the error
all i/o channel link adaptor
a symbol plane
a major vote output for ani commun

a channel buffer
underflow of bitstream data in the channel buffer
the transfer of pictur data from the channel buffer
the oper of the novel channel buffer manag scheme
the data bit
the channel buffer by a video decod
the channel buffer
the amount of memori
rate channel
pictur reconstruct
pictur data
manag of channel buffer in video decod
amount of bitstream data
a video bitstream
a transmiss channel
a novel channel buffer manag scheme for a video decod
a microcontrol monitor
a display control

a channel extend
the separ between the processor channel
the risk of data overrun
the context of an inform
the channel extend
state of the art system
peripher devic control
mode through a channel extend
link
kilomet separ
kilomet
channel extend length
a result of request for data
a processor channel
a peripher devic control

a channel for a fluid of a process
the second compon of the signal in a flow model of the pipelin system
the process of the process facil
the process control system
the inform of the process
the inform about the fluid
the first compon
method of predict mainten of a process control system
inform about the process variabl be
inform about the fluid
immin failur of the equip
fluid movement
advisori inform
a sensor element
a second filter
a second compon
a process control system
a plural of equip
a pipelin system of a process facil
a first filter
a first compon

a channel servic unit
the server interfac
the remot data
the primari data
the link interfac
system a anoth disk drive control
method for remot mirror of digit data from a primari network server
data from the primari network server over the link
commerci commun link
analog telephon line
a system for remot mirror of digit data from a primari network server
a server interfac
a safe distanc
a remot network server
a remot data
a link interfac
a convent commun link

a charact gener
video display control unit
the video signal encod
the read address inform
the charact inform
the charact gener
that charact inform
sequenc of a screen
period in a pipelin regist
period by a pipelin regist
output video signal on the basi
inform from a video memori
address unit time division manner on the basi of address signal from a memori address counter
address specify inform
a video signal encod
a video display control unit control charact
a sequenti scan display unit

a charact regist
the logic express
pushdown stack for a vector comput
logic express
error in the logic express
data into the vector regist
binari operand element
an oper element of the logic express
an error detector
a second pushdown stack
a second oper element at a top of the second pushdown stack
a relationship between a first oper element in the charact regist
a logic express
a first pushdown stack

a charg domain analog to digit convert
waveform
the equal
the digit signal
the digit charg
the analog charg domain
signal respons
digit charg
data in the form of an input analog
charg coupl devic
analog signal process circuitri
analog input
analog charg domain
a digit bit stream from the digit charg domain
a digit bit stream
a charg signal equal
a charg domain signal equal
a charg domain digit signal processor

a check
thi disclosur
the process of store oper
the present devic
single cycl store oper in a virtual memori
memori store in a memori of a comput system
a translat devic
a store command
a real address

a check for process termin
the observ that group of point
the method process visibl point
the comparison of the point
separ process
sentinel at the edg
point in the frame buffer
chang in point intens for the group of visibl point
a z buffer process

a check that each packet
the sourc user
the same group
the hub
the data concentr
the 256
that user
sourc user
secur featur
parallel oper within the control
packet from a data
maximum size space divis switch
mani concentr from each data
man
fiber optic data link
distribut network
disconnect action
destin user
data concentr at the edg of the network
control space divis switch
control of the space divis switch
connect in that switch
architectur of the control of a high perform packet
a port identif
a larg fan out distribut network
a hub
a high capac metropolitan area network
a concentr
a common outlet of the space divis switch

a checkerboard pattern
the multi processor data
multiprocessor data
method for complex data movement in a multi processor data
complex data movement pattern between the processor
a transpos pattern
a ping pong pattern
a method for complex data movement in a multi processor data

a checkpoint
timeout checkpoint format
time out condit
time out checkpoint
the time period for recoveri from an except condit
the number of clock cycl
the maximum number of instruct within a checkpoint boundari
the last checkpoint
the instruct window size
such time out condit
such method
processor state restor depend on instruct window size
processor backup
instruct attribut
current processor state
convent processor backup techniqu
convent checkpoint
checkpoint techniqu in the event of an except

checkpoint storag entri
checkpoint

a checkpoint storag unit
trap level by the old map
the unavail list
the trap stack unit
the trap stack storag entri with a current map
the trap level by the current mapping
the trap level
the state of the data processor each time a trap
the mapping
the freelist unit
the current mapping
the current avail list of the freelist unit
the current avail list
the content of the regist
the checkpoint storag unit store
the checkpoint
the avail list
number of trap level
each trap stack storag entri
each trap
each time a trap
each backup
avail trap stack storag entri
an unavail list of each trap stack storag entri
an old map
a trap stack unit
a trap stack data storag structur
a greater number of trap slack storag entri
a freelist unit
a current map of each trap level
a current avail list of the trap stack storag entri

a chien search
the small overhead for programm
the number of cell
the individu systol array
the field gener polynomi
the code gener polynomi
the basic architectur
programm systol bch decod
processor of the decod
primit bch
order of the error correct capabl t
non primit bch
multipl systol microchip with a single control
microchip
fix code applic
error correct capabl
both error
binari bch code of ani rate over ani field
a single vlsi microchip
a recurs extend
a programm decod
a key equat solver

a chien search circuit
the syndrom processor
the syndrom comput
the chien search circuit
syndrom comput
reed solomon decod
number of erasur
error valu at an error locat at each error locat
error locat
error erasur locat
erasur locat member
codeword
an erasur flag
a syndrom processor
a syndrom comput
a reed solomon decod

a child instruct in the dag
the instruct for each program segment
instruct order
instruct for each program segment
hazard includ combin of a parent instruct
hazard from a program
dag for each program
an optim apparatu i
acycl graph

a chip
main pipelin process
bu band width for memori operand access
an operand pre fetch unit
an operand address comput unit
a control inform buffer

a chip for analog
use by digit process devic
the prp
the ape
the analog
pattern recognit processor
dimension signal
current digit process technologi
compress rate
compress
charg packet
ccd base element in a semi conductor devic
audio signal
analog video compress at rate
an array of ape
a semi conductor devic
a particular embodi

each vector regist
a plural of element

a chunk valid control
valid indic
valid element
the vector regist in respons
the valid indic
the operand for success oper
the operand for oper
the last element of a group of element
the entir chunk
the avail of valid element from the vector regist
the alfu
out of order element
operand for success oper
operand data for oper
instruct in order
element address
each valid indic
an arithmet logic function unit
alfu
a vector comput with variabl memori latenc
a valu of the valid indic in respons
a valid indic
a subset of the element

a circuit arrang for parallel oper
these remaind
the smaller operand
the output of the adder stage
the output of each stage
the intermedi sum until the remaind
the intermedi remaind
the input of the adder stage
the form of intermedi sum
the final result
remaind
an exact sum of the operand
a single adder stage
a remaind regist
a fresh operand

a second circuit
a first circuit

a circuit descript
those regist
the wait factor of the data transfer
the second file
the resourc conflict
the logic templat
the gener of redund logic
the first file
the first circuit without a circuit
the first circuit
the content of the second file
resourc conflict among the point
regist in respons
mutual connect
logic templat
input in respons
determin
data propag
cycl of the regist
condit of data
circuit descript
automat logic gener method for pipelin processor
a third file
a third circuit
a second file
a regist in respons
a first file

the same main data
the integ unit
the function unit of the microprocessor
the decod in specul order
superscalar microprocessor
point function unit that share a high perform main data
multipl instruct per microprocessor cycl
multipl data width
load/stor unit
high perform superscalar microprocessor
effici use of the microprocessor die size
commun therebetween
branch predict unit
a main memori via an intern address data
a integ function unit

a circuit for thi oper
the same adder
the oper in a pipe line
result of the partial multipl
partial multipl
long integ
integ of mani figur with a small circuit scale
each adder
an upper adder in the next cycl of addit
a systol array of ident process element
a manner that an input valu

a circuit setup
the pipelin control system
the oper on the data
the microprogram
the invent further deal with the processor
the input side of the arithmet unit
the destin latch regist
microcycl
ani content for a regist
a microcycl
a destin latch regist on the output side of the arithmet unit

a circuit specif
the top rank perform valu
the execut perform
the artifici depend
set of hardwar depend
memori disambigu limit
hardwar limit
depend graph
branch predict limit
artifici hardwar depend
artifici depend
a set of perform valu
a set of artifici depend
a dynam depend graph
a depend graph for a set of comput program instruct

a circular array of receiv element
wave front curvatur
volum at variou posit
variou perspect
tomograph imag
time histori
the volumetr imag
the time histori of each element
the reconstruct processor
the reconstruct process
the perspect processor
spars circular array of receiv element
object in thi volum
no approxim
huygen principl
fresnel
fraunhof in the reconstruct
ellipsoid backproject
echoe
dimension volum
dimension display
dimension imag devic
dimens with a single puls of energi
axicon
a wide solid angular volum
a single monopolar
a simple time of flight algorithm
a reconstruct processor
a perspect processor
a larg diamet
a digit memori

video inform
time synchron
asynchron swing
an mpeg video decompress method
a parallel huffman decod
a common process block

a circular queue
the video scan line
the pixel on the scan line
the last polygon
the command from the host
that processor
synchron with the video scan
real time color graphic
polygon command
painter
each scan
each pixel processor in turn
each pictur element
color if the painter
a special command
a plural of polygon
a plural of microprocessor
a line command
a color graphic system

a class descriptor
object model for java
object data
o3
interfac refer
each object
each class

a classif key field
the search field within the lookup tabl
the respect search field within the respect lookup tabl
the respect search field
the manner of further process
the lookup tabl
the frame
the event the searche
the basi for a further search of the search field
receipt of a frame at an input port of a frame processor
frame classif
each respect address
classif key field
classif key
a search field
a plural of lookup tabl
a frame processor in a comput network
a compact classif key i

a classif piplin
vector attribut
the number of data item
the compar unit
the classif unit
the classif pipelin
the classif data item from the regist
the classif data item
respect bin chain
processor for vector data classif
compar chain
classif data item into the regist in respons
classif data item
an array of compar unit
an array of classif unit
a refer valu for comparison with the classif data item

a classifi block
the system databas
the same resolut
the product design
the process engin
the inspect resolut
the inspect gray scale signal i
the full imag
refer imag of the product
product inspect data
inspect system
inspect imag
inspect data
imag resolut becaus the refer
gray scale inspect imag
entri into the defect memori
each defect type
an electron registr subsystem
all parallel defect detect channel
align the refer data
accur represent
abnorm between refer
a separ channel
a raster manner
a defect memori

the merchant
the internet

a client
the server applic
the request for connect
the client termin i a network
the client termin applic requir
the client applic in the client
the client applic at the server
the applic dispatch
server
the switch subsystem
the requestor
the memori of the control
the connect of a multitud of request per link
switch server
output link
one of a plural of output link
one of a plural of input link
low end high perform switch subsystem architectur
high perform switch subsystem
an interfac protocol
altern action
a request server
a data structur for the switch subsystem
a cross bar switch under the control of a control
request from the client applic on behalf of the client
more server
client applic on server if client
client applic on client if client
an applic dispatch at the server
all futur request from the client applic
a server applic in the server
a server applic at the server
a plural of client
a pair of action
a connect with a server
a client applic in the server

a payment method
the instrument in the wallet
purs
the display screen
secur author for a particular instrument
payment instrument in network electron commerc
payment instrument holder
other form of payment
money
electron approv result in the gener of an electron transact
credit card
choic
electron approv for the transact
articl of manufactur for the use of payment instrument holder
an icon
an electron monetari system that emul a wallet
an electron monetari system
a summari of the good for purchas
a purs
a payment instrument
a password
a graphic represent of the payment instrument
an appropri indicia
articl of manufactur for network electron author
payment
an electron approv for the transact
an author instrument

a client over a first commun link
the gateway for further process
the appropri credenti
storefront
queri the vpo system
process custom satisfact inform
payment administr inform
more merchant and/or consum
merchant specif transact
inventori control inform
host applic
credenti
queri the server
audit inform
ani other comput
a ssl
a server that commun
a particular merchant
a merchant
a consum
articl of manufactur for remot virtual point of sale
a gateway over a first commun link

a client subsystem
transfer of data between a workstat
the workstat in order
the workstat
the transfer of data from the workstat
the remot comput
the privat network
the first workstat
process access right
network interfac
internetwork
extern network
data between the privat network interfac
a server function
a remot comput
a privat network interfac
a privat network
a filter function

a clock circuit
the system clock rate
the n phase of the system clock
n phase
n access
multipl clock signal
multi phase multi access pipelin memori system
multi access pipelin memori system
each system clock signal period
access for each processor
a system clock signal
a pipelin memori

a clock control
trace control
microprogram storag
facil within a comput develop system
breakpoint control
a plural of vlsi emul
a plural of storag devic emul
a plural of emul
a logic group of facil within a comput develop system

the phase of an intern clock
an extern clock

a clock gener circuit
the voltag
the phase of the intern clock
the phase of the extern clock
the phase detector
the frequenc of the extern clock
the frequenc band
the error signal i
the differ in phase
the delay of an extern clock
small rang
other circuitri
oscil
onli control the frequenc of the intern clock
extern clock
error signal i
a user with data
a signal from a regist
a plural of discret frequenc band
a control input of a voltag

a clock gener in the counter circuit
the stage output in respons
the asymmetr clock
stage output
set of switche in each stage
set of switche in each pair from the stage output
output stage
isol switche decoupl
high speed count
asymmetr clock signal
a stage output in respons
a seri of regist
a counter circuit

a clock input
the static stage
the current pulldown path
the amplifi stage
high perform vlsi circuitri
current pulldown path
an amplifi stage
amplifi base flip flop element
advantag featur in high perform microprocessor
a static stage
a static latch
a small hold time
a short latenc
a dual output amplifi
a current-sens static amplifi base flip flop i

a clock optim approach
the coverag data
some pixel region
separ color
pixel data in a graphic
pixel circuitri in a hardwar optim approach
pixel circuitri
list of pixel fragment
hardwar requir
final color valu for a pixel
depth
unnecessari process
the pipelin sequenc
system with reconfigur pipelin sequenc
stencil test
pixel elimin sequenc
opengl
graphic processor
complianc with specif
common alpha valu
color contribut for fragment layer
alpha valu from the pixel fragment in a fragment list
alpha valu for sub pixel region of a pixel
alpha valu a each fragment layer
alpha accumul
a single color accumul oper for a pixel region
a geometr primit cover sub pixel region of a pixel
a coverag mask

a clock period of p
the ram respons time
readout of the random access memori in parallel into a read data
pictur element
parallel into a random access memori
p n
digit frame processor pipe line circuit
a readout data
a readin regist
a plural of digit word

a clock rate
mhz
vlsi circuit structur
the principl
the maximum extent in order
the jpeg baselin imag compress
the entir i
the circuit structur
jpeg imag compress
frame per second
an input rate
a single vlsi chip
two dimension invers discret cosin
the 2-d idct processor of the invent
cosin angle index gener
a two dimension invers discret cosin
a symmetr kernel
a pixel rate
a coeffici by coeffici 2-d idct algorithm

a clock rate of a machin cycl
the read oper
the clock rate of the machin cycl
pitch
half period therebetween
half of a total time period
half of a total time
equal address
all odd number element of the vector data
all even number element of vector data
a read pitch of the vector regist
a read address gener
a phase differ

a clock signal i
the logic circuit
that determin
phase relationship
a plural of output signal in respons
a fals lock detector for use in conjunct
a fals lock detector

a cmo vlsi chip
the type of motion
the sobel edg valu in the previou frame
the sobel edg valu in the current frame
the same posit
the motion detect processor in parallel in a pipelin fashion with no feedback
the differ pictur gener
the differ pictur
that region
sobel oper
real time respons
motion detect processor
method for dynam scene analysi
current frame pixel valu
current frame
compon label of the differ pictur
compon in the differ pictur
compon hardwar
circuit architectur for dynam scene analysi
ani case
an altern arrang
algorithm in order
a sobel edg detector
a seri of motion detect processor
a differ region of the differ pictur in order
a differ pictur

the gener purpos processor
a gener purpos processor

a co processor interfac
vector of length
vector compon
thi parallel execut approach
thi interfac
the three dimension vector
the sourc multiplex
the destin multiplex of the co processor use full cross bar switche
the datapath of a three dimension vector
the 3dvcp
scalar while the gener purpos processor
pipelin the program instruct in stage in addit
parallel execut unit
k execut unit
j
expoit the intrins parallel
control line of the data
a three dimension vector co process system
a regist to regist architectur

a code convert
variabl length huffman code by puls
the root node
the path from a decod
the path end node
the output code
the next convers
the input of an encod
standard code by connect of the huffman code
standard code
revers binari tree fashion with logic path between leaf node
huffman
code output
code convert for data compression/decompress
branche of the network
an or gate i
a puls from the root node
a network of logic circuit
a feedback loop
a common root node

a code fragment of loop instruct
zero overhead loop
thi capabl
thi bit
the repeat loop
the repeat count
the repeat bit of the penultim loop instruct
the repeat bit
the pc
the execut code fragment
the decrementor with the pc incrementor
the code fragment
the assembler/compil
the assembl
the address of the first repeat loop instruct
refetch the first loop instruct at the end of a repeat
overhead loop
n time
iter n
increment the repeat counter
each loop instruct
compact system
all system
a repeat end regist
a repeat bit
a decrementor that decrement the repeat count from n each time the loop

a code unit for a parallel pipelin processor
the translat of convent address coupl
the mechan attempt
the concaten
system into gener regist number
system concaten
languag code
data in the gener regist
data array in memori
an address coupl associ memori
acam for use

a codec
the write of an address into the address buffer
the oper of the codec
the imag data input buffer store
the control inform for a block
the compress
the address buffer store address
sequenti
transfer action
the separ multipli
the instruct store
the arithmet capabl of the processor
phase pipelin
own instruct store
extens diagnost capabl
dma mode
certain task
action in differ segment of the data
a single chip implement of an architectur
a full arithmet logic unit
each block of imag data
decompress of imag data
block of imag data
an initi address of a block of address within an imag memori
an imag data output buffer
an imag data input buffer
an address buffer
accord with the read out inform
a local control
a first process stage
a discret cosin transform quantiz process
a discret cosin transform process

a coder/decod
vertic synchron signal
the stop of the transmiss of pixel data from the codec
the scaler devic
the scale of the video data
the rate of display
the interfac between the scaler devic
the codec devic
assert of the stall signal result in the suspens of the transmiss
a threshold level
a stall signal i
a signific increas
a scaler devic
a frame buffer within a display adapt of a data

a coeffici address pointer
the transfer buffer
the coeffici data
stage in the same process unit
new coeffici data
method for coeffici data
method for a digit signal processor
effici data
coeffici data
a valu of a program counter
a transfer buffer at an instruct read stage
a read instruct of the coeffici data
a microcomput determin
a coeffici data memori by the read cycl
a coeffici data

a coeffici memori
the sum of product comput 28
the gener use memori
the extern memori input/output interfac circuit
the arithmet logic unit 26
digit signal process unit
arithmet process effici
anoth data
an extern memori input/output interfac circuit
an audio/interfac circuit
a sum of product comput
a host interfac circuit 34
a gener use memori
a gener data

a coeffici memori address regist
the valu of the output data
the result valu in the address regist
the flow of a program
accord with the result of the decis
a read address of the coeffici data memori
a flag regist in accord with the result of an arithmet oper
a condit judgment

a coeffici regist
the oper process on the music tone signal
the oper process on data
the microprogram memori in accord with a second address
the dsp
the delay memori
the content of oper process
the coeffici regist in accord with a first address
storag capac of the microprogram memori
set of coeffici
second address signal
result of the oper process
readout
plural seri of music tone signal
plural oper for plural tone in respons
oper of the filter
oper of the delay memori
oper command
each program
an electron music instrument
a delay memori

the regist cach
a regist cach

a coher mechan
valu from regist cach
unit with a plural of pipelin
the regist file at a time
the plural of pipelin
the coher protocol
sourc regist valu
ownership protocol
each regist cach store
destin regist valu from a regist file
coher among the regist valu in the plural of regist cach
coher among the regist valu in the plural of pipelin
coher among regist valu in the pipelin
address valid copi of a regist valu
a varieti of coher mechan
a new protocol

a coincid
true/fals in tf
true/fals
the shadow regist file
the result data in shadow regist file if the instruct
the result data in sequenti regist file if the instruct
sequenti regist file
entri in tf
condit in parallel
an execut control circuit
a tf regist
a shadow regist file
a sequenti regist file

a collect
weight set
the optim weight
the lowest cost
the collect
subsequ weight set
rapid identif of the overal optim weight
rapid identif of the optim weight
initi weight
each collect
differ collect
an apparatu for cost

a collector for the result
visibl regist
the result of the execut of instruct
the result of the execut of each instruct by an execut unit
the order of instruct
the oper code
the instruct execut stack
result of the execut of instruct into memori in program order
order of issuanc by the pipelin
first out basi
collector control
collector
central process unit of a digit data
an instruct execut queue of the collector
a differ set of instruct of the instruct repertoir of the processor

a collim len
the wall of the pipelin
the volumetr flow rate of ga
the veloc of the particl
the presenc of turbul in the pipelin
the output of the photodetector
the flow rate of the ga
the flow of ga in a pipelin
the apparatu measur the flow of ga
that case
pre record holograph film
photodetector
particl in the ga scatter the light
optic flowmet
holograph imag at sever differ radii in the pipelin
engin intak
discret laser spot in the pipelin
differ part of the pipelin
cylindr ga pipelin
aspect of thi invent
anoth collim len
an optic transmitt
an optic receiv
a laser diod array

a color graphic pipelin
visual qualiti of a color
the encod
the dither nois valu
the color valu
neg dither nois valu with the color valu
mechan quantiz
mechan alias the color valu with other color valu
independ optim of each color
each encod
each color valu in pixel data
cutoff valu
color valu for storag in memori
color rang
better edg detect in a color recoveri filter within a decod of the pipelin
an adder mechan
a separ encod with a dither
a dither tabl
a compar mechan
a color valu

a color laser copier
variou pipelin structur
the jpeg
the dtp system
realiz
pipelin structur for full color comput graphic
imag creation
graphic imag in band across a page imag with the imag
adct compess
a workscreen display
a keyboard
a full color high resolut graphic system
a full color desk top publishinbg
a digit

a colorburst calcul algorithm
the phase of the colorburst signal i
the phase compon
the ntsc composit video
the colorburst calcul
the chroma signal i
the chroma
signal by a y/c separ algorithm
portion of plural cycl
nois reduct of cyclic signal
major logic state
demodul the chroma
an edtv applic
a synchron vector processor

a column address
the input of the column address
the dram
the command word in each command packet
the command word
the column address bu drive a column address
the adder increment the column address at the output of the column address
respect storag unit
multipl memori address
dynam random access memori
command packet
an increment
a plural of storag unit
a plural of command word
a plural of column address
a common column address
a column address decod

a column flag select
the same templat control signal
the data output
the array of imag data
other control signal line
method for imag data array
method for an array of imag data
element shift imag data from the data input
demarc the row of the imag data array
a mask process element

a column multiplex
the unit of time
the same number of latch circuit
the row driver
the row decod
the novel memori system
the memori system for the improv of the perform of the memori system
the column sens amplifi
the column multiplex
serial fashion
more data
latch circuit
high perform memori system
data from a memori array
column sens amplifi
column address
a unit of time
a row driver
a row decod
a result of the use of these latch circuit in a memori system
a plural of standard element
a novel memori system
a convent memori system

a column neuron
the total connect of each neuron
the neural comput paradigm
the hopfield model
snap
virtual neurocomput architectur for neural network
tsnap
thi virtual neural process
the virtual neuron
the number of physic neuron
the number of neuron
the architectur for a scalabl neural processor
network simul
gener virtual architectur approach
both snap
a triangular scalabl neural array processor
a third approach
set of input function element
scalabl
the perform characterist of a crossbar
the interconnect scheme
the cost advantag
system perform a addit common storag control modul
multipl instruct processor
input/output subsystem in a symmetr multi process environ
bar type storag control
a new storag control
a high perform interconnect scheme
product summat
orthogon row column neural processor
neuron valu
neural state calcul
neural network architectur
network model
multipli element
larger network
intens system
input weight multipl
herein
each neuron
complet connect among the neuron
an orthogon row column relationship of neuron
all neuron
a uniqu intercommun scheme within an array structur
a second cycl a a column element within an input function
a row neuron
a neuron valu
a first cycl a a row element within an input function

a combin graph
the program in the combin graph
program through reduct
combin reduct
a program into tupl
a plural of process unit

a common memori
timer processor
the instruct of either processor
stage pipelin arrang
some complex algorithm
servic of input/output pin
separ program counter
multipl instruct routin
length loop of single instruct
instruct the other
i/o pin
high resolut
a main microprocessor of the burden
a common execut unit

a combin of a bu control unit
the dmm
each dmm
dmm
bu share control
bu control for a plural of digit signal processor
an input frame memori
a plural of independ common buse
a plural of digit signal processor
a plural of common memori
a multiprocessor type time
a dsp
a combin of a task control unit

a combin of an instruct
the use of anoth resourc
the use of an oper unit
the resourc in a plural of stage
the decis of the detect circuit
instruct in a pair of instruct regist

a combin of delay
serial data in revers binari order
normal binari order
data reorder system
data in revers binari order
data in normal binari order

a combin of low latenc
the number of time that a messag
the notif of the origin that transmiss
the control function
the blockag of the multistag network
the backward path
the amount
retransmiss
probabl of blockag
path in the multistag network
particular applic in the interconnect of parallel comput
no buffer
multistag network
multipl return path
higher util of the data
higher util of data
anoth attempt
a multistag network

array processor
an array processor

a combin of plural type of input vector data seri
type of input vector data seri
type of input vector data
the overal array processor
the multiplex in the form
the combin of the vector data
plural process element
parallel process of pattern
input vector data
data input/output to/from the i/o
control method
autonom control
an input vector data
an i/o data
a select of the input vector data
a posit of respect vector data
a higheffici util of hardwar resourc
a high effici

a combin of signal
the microcod
simul algorithm
signal on the data
conjunct with a master comput
a memori address gener

a combin of signal from the leak
the like presenc of a leak
size of ani leak
particip in the leak detect procedur by an expert
much greater quantiti of nois
method of data
leak in pipelin
data from a plural of sensor
commun of data between the base station
base station
a plural of acoust sensor
a distant supervisori station

a combin of variant of smaller size sdct
the lower order sdct
the invers quantiz stage
the invers direct
stage pipelin architectur of the present invent
slow intern clock
sdct
rapid implement
larg volum imag data in real time
invers sdct coeffici
invers sdct
effect of the coeffici
advantag of the recurs properti of the sdct
a larger size sdct
a high throughput of imag data

a combinatori circuit
the processor regist data
sever set of data
proper order
output of individu processor
order with respect
binari control signal
an asynchron form of pipelin processor
amplifi
a storag capabl

a command control
verifi that a plural of pipelin stage
the statu area of the same command
the pipelin bit
the execut command
the correct order
the command queue
state of the execut of the command in the asynchron comput unit
pipelin bit
oper of the execut of the command
oper of a data
asynchron comput unit
asynchron comput command
asynchron command
a statu area
a queue verifi

circuit within the pipelin
circuit in the pipelin

a command for setup
the pipelin command
the data from the pipelin
the command from the data
the appropri context
that command
setup
oper of the pipelin
identif valu with a tag field in the command
data in a common pipelin path in a high speed comput graphic system
accord with the current configur of the pipelin
a similar determin
a pipelin data flush i

a command on the command
the variou bu compon in the same clock cycl
the third data sourc
the second data sourc
the overal effici of the bu
the data sourc
differ channel
deliveri of data for the differ channel
data on the data
data destin at a time
data destin
channel between data sourc
accord with the bu protocol
a third data sourc
a particular channel
a fourth data sourc
a data sourc of a second channel

a command preprocessor
the varieti of system constraint
scan interpol
geometri input data format into a standard format
function for separ portion of a triangle
dimension graphic function
architectur for a high perform
a set of float point processor
a set of draw processor
a graphic acceler

a command under test pass through the processor result in the signal at the test point
the store of the signal by the snapshot regist
the signal at test point
snapshot command
replac circuit unit in respons
fault in a processor
each snapshot circuit
each replac circuit unit
an immedi snapshot command
a snapshot regist
a snapshot circuit
a plural of replac circuit unit

request for access
a plural of memori bank

a command/address bu line
the other group
parallel process for data
memori control system
even memori bank
data bu line
anoth request for access
a single access request for doubleword data transfer
a read data bu line
a memori access control system

a common area
writing
the subsequ data
the mode of the access
the memori access unit store inform
the memori access unit store
the memori access unit access the cach memori
the content of the cach memori in coher with the content of the main memori
the circuit scale
the cach memori address by address
same area of the cach memori
recent access mode
recent access
parallel reading
differ address
coher cach
area of differ main memori
an access mode
a specif process
a part of the address
a data item

a common bu
the simd type parallel data
the optimum parallel process system
the mimd type parallel data
suitabl processing
suitabl applic field
simple processing of a larg volum of data
simd type parallel data
processing
mimd type parallel data
high speed data
demerit
data stream in the parallel data
complex processing of imag
complex processing of a small volum of data
both merit
an effect time
a wide rang of applic field
a single instruct stream
a simd unit with a mimd unit
a simd type parallel process unit
a practic time
a mimd type parallel data
a convent comput

a common bu structur
unit to unit inform transfer
transfer cycl
the updat element
the updat cycl
the second memori unit
the onset of the updat cycl
the onset of the memori
that first signal
sequenc in differ respect time interv of the transfer cycl
second memori unit
plural time interv
plural phase
inform from the first memori unit
inform between function unit
dynam memori element in the first memori unit
a transfer cycl
a peripher control unit
a memori updat element

a common build block of synaps processor
virtual size
the synaps processor group
the synaps processor
synchron problem
synaps processor architectur
scalabl flow virtual learn neurocomput
own extern memori
intern
wavefront array processor
the ready
the presenc of second handshak
the latch with data
the issuanc of first handshak
the handshak signal
the handshak port
the adjac cell
room in the buffer
data from the adjac cell
bu configur for distribut of data between the handshak port
anoth handshak port
an adjac cell
access data from the buffer
a wavefront array processor
a sourc statu signal
a sink statu signal
a handshak port for asynchron data
a data sourc
inner squar
direct execut capabl
complet connect with high perform
capabl of back propag for virtual learn
array separ
a scalabl virtual learn architectur
a scalabl hybrid control flow/data flow
a scalabl flow virtual learn neurocomput system
a hybrid control flow/data flow architectur with extern memori access
a gener purpos virtual learn machin

a common central process unit modul
the saep
the algorithm for half
sum with an absolut valu
sum of the differenti voltag
number of analog signal
micro programm method
high speed/high resolut analog comput
high sample rate
hereinaft
differenti voltag
certain function
an alarm evalu
alarm electron processor

a common control circuit card
the ram buffer
the need of the individu type of peripher termin unit
the common control circuit card
the common control circuit
sequenc of micro code word oper
prom storag
processor in an i/o subsystem
micro code oper for execut by the peripher depend board
function of a varieti of data
common front end control for a peripher control
area of a ram buffer
address sourc from a host system address
address multiplexor
a peripher depend circuit board
a peripher address
a main host comput system

a common control in order
variou oper
the variou imag
the output of each circuit
the next circuit in the pipelin
the individu process circuit
the imag element
the data between circuit of the pipelin
line of the imag
end of window instruct in the appropri place in the sequenc
duplic
delet
the systol pipe
string of data
string
stream of input charact
set of pointer
portion of the input stream
pointer in place of the string
parallel systol pipe structur
parallel systol pipe array
novel method
decompress of the stream of pointer
data string in place of the pointer
data compress by textual substitut
an input end of the pipe
a stream of input charact
a dictionari of string of previous read input charact in associ
a dictionari
a data compress system
a sequenc of program instruct

a common data
the result data word from the arithmet section
subsect
data word with anoth data word
an express
an arithmet section
a result data word

the null state
a threshold number
null convent signal
null convent logic system

a plural of input
all input
a null state

a common input
the simultan process of differ size fft
overal hardwar requir
normal order input
input data set
fftmp of the present invent
fft of variou size
embodi the fftmp
element for simultan process
effici share
decim in frequenc fft
both decim in time
a fast fourier transform
a delay commut

a common integ denomin
the origin numer
the integ denomin
precis squar root
point represent of the numer
point quotient
point hardwar
point approxim
numer
the nth solut
the next approxim
the new solut
the equat on the data point
th approxim
optic wavefront data
number of data point
a set of equat in an array of parallel processor
multipl integ quotient of integ numer
microprocessor integ divis oper
an initi approxim
a finit power seri
a final reciproc i

a common interfac
the select of a reconfigur
the implement of a particular instruct
the gpim
the drpu
the dou
the aou
reconfigur process unit
reconfigur oper
program execut in respons
parallel commun
more interconnect i/o unit
each t machin i a data
each reconfigur direct refer a configur data
each reconfigur
each  machin i
data comput
changeabl intern hardwar organ
an address oper unit
address comput
a set of program instruct
a set of i/o devic
a set of i/o
a second local time base unit
a scalabl interconnect network
a reprogramm logic devic
a reconfigur
a master time base unit form a system
a gener purpos interconnect matrix
a first local time base unit
a drpu hardwar organ
a data oper unit

a common macro interfac
vhsic hardwar descript
vhdl
transfer of data
traffic collis
the industri standard hardwar design languag
the freeway
the effort
the common macro interfac
sever chip
macro
the sourc macro until all data input
the macro
self time control circuit for self reset logic circuitri
all data input
a self time control circuit for self reset cmo logic circuitri
a particular macro
a macro
a complet signal
front of everi slave resourc
design featur
complet system modif
commun problem
a freeway system within the interfac
a common protocol
a common macro interfac between chip

a common main memori
the unit of memori alloc in the comput system
the same locat in the lock directori
the same block of memori
the parallel oper of a plural of central process unit
the lock request
the lock bit
the level of individu cach block for the cpu
the denial
the cach block
that state until the unit
memori address a an index into the directori
memori access oper in multiprocessor system
lock bit in the lock directori in the scu
lock bit
i/o unit
granular
fair for the process
a system control unit
a reserv list
a plural of lock bit
a lock directori
a first-com first serv basi
a directori of lock bit

a common memori in a multiprocessor system
the plural of processor in the multiprocessor system
the global regist system
the common memori in order
the common memori
resourc circuit
more regist
logic oper on a data
indirect address
global regist in a multiprocessor system
global regist a part of an atom oper
direct address
coordin among a plural of processor
arithmet
a single read and modifi instruct
a global regist system

valu a operand for thread of comput
the thread of comput
the data processor that a thread of comput
system with synchron coprocessor for multipl thread
remot node
other node of the system
new thread of comput
messag with data valu
each block
block of code
a thread of comput
a synchron coprocessor
a node design
a local virtual address at the remot node
a global virtual address

a common memori with the translat from a local virtual address
the synchron coprocessor
the start messag
a local physic address
a data cach stage

manag
smart object memori
pipelin coher
linkag
worst time durat
the next stack oper
high level languag procedur
exceptional/condit oper
data pointer
auxiliari stack
altern oper
a system look up tabl further prefetch
a method for high level languag procedur
circuit system architectur for document instruct

accord with the invent
transfer of larg data block
the screen system
the pipelin bypass
the hardwar implement
reduct in time
pipelin latenc
hardwar solut for window rel render of graphic primit
gross overhead processor time for the graphic pipelin
graphic window system
graphic primit
graphic pipelin bypass buse
elimin of pipelin
accord with the invent exhibit signific pipelin effici

complex function
addit hardwar

a common physic regist pool under control of a regist manag system
type of architectur
these milli mode instruct
the millicod
the milli mode onli instruct with standard system instruct
standard system architectur
standard architectur instruct
pipelin reset of the facil
pipelin reset
own set
millicod routin
explicit updat of gener purpos regist
dataflow
thi design effect
more successor instruct
more predecessor instruct
larg number
instruct indic
input/output circuitri
graph
total object treatment of all data
total object
the occurr of some error condit
the invent a a direct flow of data between processor element
specif identif
specif
the state machin a task
the state machin a a decis tree of ani length
the select criteria
the recognit instruct
the reason for select of a packet
the content of each packet meet select criteria
select requir
recognit instruct
program count upon accept
plural distinct criteria
packet filter engin
key code
interfac processor
inform packet broadcast on the system
exampl by the state machin
examin of arbitrari section of the packet for equality/inequ
data requir
byte posit
bit mask comparison
a seri of recognit instruct
a digit commun system
process structur
job complet
intervent by control element
instanc identif for a single member of a particular specif class
function process element
correct result
certif of result
all object
account entri
a process network structur
a particular job
element transact on data
each successor instruct
each predecessor instruct
circuit chip a a basi for effici high perform comput
associ of execut compon
ani pair of node
ani other process element
an arc
a transmiss path
a static dataflow architectur of the type
a predecessor successor pair of instruct
a plural of dataflow
a novel comput design
a distribut of instruct
an altern instruct architectur
an altern architectur that the processor
a set of regist operand regist

a common video interfac
video stream
video data rate
the submodul
pixel data in the video signal path
pattern recognit submodul
option within each submodul
option addit imag
complex special purpos imag
ani modern microprocessor for overal system control
a wide varieti of imag
a video stream
a varieti of submodul
a uniqu system
a stream
a processor interfac

a common writeback path
writeback conflict between execut unit
the dispatch of variou instruct
the depth
multistag execut unit
execut unit pipelin
conflict between execut unit
a writeback conflict
a shorter pipelin

a commun link
transduc
those portion
the effect of the magnet flux on the output signal
the distribut function of the electromagnet field paramet
the convent techniqu
portion of the magnet circuit
portion of a number of pipelin
perimet of the pipelin
nondestruct electromagnet inspect of pipelin
magnet flux excit
magnet flux
magnet circuit
hard-to get at portion of pipelin
electromagnet field paramet over the whole length
current over the pipelin
coil
atom power station
a system of magnet field
a system of induct coil
a portion of a pipelin
a devic for nondestruct inspect of pipelin
a data present unit

a commun network
use in commun network
the process of outbound inform packet
the network commun medium
sublayer
real time a each packet
outbound inform packet
option data path
local encrypt
in line process entiti of a network architectur
in line encrypt
decrypt of data packet
decrypt for variou purpos
data portion
data interfac
cryptographi processor
cryptograph
both direct
a revers direct
a media access control
a full duplex cryptograph processor
a fiber

a commun path for commun
the processor memori element
scalabl node of the comput system
processor memori element within the node
processor memori element
parallel array processor
a plural of scalabl node
a plural of commun path for commun within a node

the second memori
the first memori
a second memori
a first memori

a commun receiv
the new oper system into the first memori
system of a comput system
flash memori
data bitstream
cach memori of a video processor
a satellit busi receiv

a compact method
y direct bit
workstat
major axi
vector in the frame buffer
the pictur processor a a first word
the next pixel
the major axi
the first word
the first pixel of a vector
system for use
such axi in the first word
point of the vector
pixel valu along the vector in the frame buffer
pipe stage with a fifo at each stage
off screen memori in commun with the pictur processor
local display bu architectur
downstream stage in a direct
commun method for raster display
buffer control circuitri
address/data
a second word
a pictur processor
a minor axi bit
a hold
a high perform graphic

a compar circuit
the second way of the cach
the second way
the first way on the cach miss in the second way
the first way of the cach
the compar circuit
select circuit
second way
miss determin in other data set
determin circuit
activ a miss
a translat look asid buffer
a hit indic circuit

a compar comput branch sequenc
valu of the variabl
use on a compil
the valu of the variabl at the end of the compar comput branch sequenc
the temporari variabl
the previou valu of the variabl
the previou execut of the sequenc
the latter comparison
the instruct of the comput compar branch sequenc
the first time the sequenc
the current valu of the variabl
the condit branch
the compar comput branch sequenc
more variabl
more temporari variabl
machin code
execut of the loop
an optim method
a comput compar branch sequenc in a loop
a comput compar branch sequenc

a compar oper
the second bit
the comparison result of a compar
signific bit of the output digit signal
output switch circuit
output in respons
lower order bit
an a/d convertor
addit compar for use
a/d convertor of the pipelin type

a comparison analysi of the output despit the possibl of unpredict data
verif of a cpu
unpredict result
unpredict event
the same set of input stimuli
the natur of the refer model
the model
the comparison output of an abstract refer model of the circuit
the circuit under test
the circuit design
a refer model

a comparison instruct
select enabl

a comparison of rate of chang of pressur
wake up timer
the first test
sever differ test
reset microcomput
pressur data
microcomput
method for detect of leak
irregular oper
interv for addit pressur data collect
interv comparison
instantan pressur
ani test
and/or actuat
a wake up timer
a powerdown mode
a leak

an attempt
the system memori

a comparison of the attribut word of the candid instruct
the other instruct
the extent
represent of each object code instruct in a small sequenti group
potenti conflict
object code instruct
more other instruct in the buffer
hardwar pipelin break
attribut word
a pair of attribut word
a compil modul

a comparison of the current pixel count
video overlay
un display pixel
transpar block of crt
the width of the graphic
the pixel path by a pixel mux near the end of the graphic pipelin
the pixel mux
the pixel compar near the end of the pipelin
the pixel address of the start
the movi window
the graphic pixel
the graphic pipelin
the graphic memori
the end of the line
the crt fifo with pixel underneath the movi overlay
other requestor
other request
non display pixel
movi portion of the screen
movi pixel for display
movi pixel
graphic pixel
full access
either graphic pixel
dummi
boundari of the movi window
a movi window over the graphic pixel data
a movi sourc
a horizont line
a crt fifo in the graphic pipelin
a comparison of the total

a competit for a regist
the parallel of a program
the order of prioriti
simultan execut of a plural of command
parallel oper processor with second command unit
oper command unit
function unit in parallel without ani conflict
a prioriti score board

a compil step
the tessel step
the primit i
the primit first i
the nurb surfac
the graphic primit i
the complex of tessel
the compil step
subsequ view
rendering
phase travers step
nurb surfac
nurb
heavi chang
creation time into a form
a uniqu graphic pipelin
a substanti portion
a display step

a complet deadlin of the first instruct schedul
the second instruct schedul
the reschedul of idl slot
the presenc of hardwar lookahead
the idl slot
the first instruct schedul
the first basic block of instruct
the first basic block
the complet deadlin
rank
program product for instruct
list of the dag node
idl slot
execut by a processor
each idl slot
deadlin
complet deadlin
an instruct in a second subsequ basic block of instruct
an idl slot in a first instruct schedul of a first basic block of instruct
a second instruct schedul
a rank of each node of a dag
a lookahead buffer
a greedi schedul

a complet of the context alter instruct
the shadow machin state regist
the second state in respons
the first state of the shadow machin state regist
the first state of the machin state regist
the context alter instruct
accord with the second state of the shadow machin state regist
accord with a context
a superscalar architectur
a shadow machin state regist in conjunct with the machin state regist
a second state in respons
a result context synchron oper
a machin state regist
a first state of the machin state regist
a context synchron oper within high perform processor
a context of the processor
a context alter instruct within a processor
a context alter instruct

a complet queue in respons
processor resourc in a data
numer non interrupt instruct
non interrupt instruct
complet of non interrupt instruct befor the instruct
buffer in respons
an interrupt instruct
a single interrupt instruct
a processor resourc snoop
a non interrupt instruct

a complet set
the pipelin stage name
the loadx signal
the detector of the except condit
that except
method for processor pipelin control by select signal deassert
loadid
fast pipelin control signal
except condit in term of the event
deassert all loadx control signal for stage
a processor pipelin control system

the memori control
a memori control
the variou other block
the next state machin
the later portion of the cycl
the earlier portion of a cycl
task on the next cycl befor the state machin
small portion of the overal oper
next start
maximum use of ani processor
main block
interdepend state machin
interact
each state machin
each memori devic
the final output of the address
control signal for the dram devic
a similar fashion
a larg number of cycl
a host block
a front end block

a complet set of program address
the processor of the present invent
the plural of execut unit for execut
the addit of task tag inform in the program flow
that task
task tag
process util of execut resourc
other process
memori manag unit that retriev an instruct from memori
independ control of the program flow
gener data regist for each task
each set of regist
control regist
concurr multitask in the superscalar uniprocessor
concurr multitask in a uniprocessor
concurr multi task process
ani result data
an instruct fetcher
a task tag
a superscalar uniprocessor
a plural of task

a complet state
the set of macroinstruct
the output of the prioriti encod
the output from the prioriti encod
the next in line macroinstruct
the microinstruct of the next in line macroinstruct
the microinstruct of a next in line macroinstruct
the instruct size regist
system out of order execut
microinstruct among the set
locat of boundari between macroinstruct among the set
input from the result complet regist
in order complet of a set of macroinstruct
an occurr
an instruct size regist
a set of microinstruct
a retir control
a result complet regist
a plural of entri field

the gpr
a gpr

a complex specifi
the use of the sourc counter
the use of the counter
the sourc counter for each gpr
the sourc counter
the destin counter
the complex specifi unit a the execut unit
sourc operand from the gpr
regist conflict scoreboard
refer count
gpr a a sourc operand
gpr a a destin operand
each time that the execut unit
each time that an execut unit
each time that a specifi
down counter in the complex specifi unit
destin count from the data depend scoreboard for a gpr
a sourc operand from the sourc counter
a sourc counter valu
a sourc counter
a read of a gpr
a destin counter valu
a destin counter for each gener purpos regist
a data depend scoreboard
a data depend conflict
a complex specifi unit

a compon
the op code for the next instruct
output a control signal order execut
microprocessor with memori
instruct data for a second cycl within a first machin cycl
each instruct cycl
cycl at the begin of each instruct cycl
counter valu

a composit
the third tag
the third object
the second tag
the second object
the fourth tag
the fourth object
second object
high perform multipl layer
a third tag for the third object
a third object
a second tag
a second object
a fourth tag
a fourth object
a first object

a composit circuit model
weren
transit
the target circuit
the state bin transit relat
the represent of the reachabl state bin
the environ circuit model
the composit circuit model
state bin
more simul
model the behavior of input
measur of the test coverag of digit simul of electron circuitri
measur of digit circuit simul test coverag
implicit fsm represent
circuit state
bdd
an environ circuit model
allow transit among user specifi set of state
a target circuit model
a state bin transit relat
a represent of the reachabl state bin

a composit read mask
the read mask
the modif of the content
the content of a gener purpos regist
respect composit mask
not yet execut instruct
multipl gener purpos regist
individu read
execut of such instruct in a digit comput
each gener purpos regist

perform improv
use in digit data
thi latenc reduct
these hazard
the instruct execut latenc
data depend hazard
compat with previou implement
an ident architectur
a multi function alu

a compound instruct
the origin set of instruct
the object code result
the execut of the compound instruct
select simultan parallel execut by execut unit
scalabl compound instruct
parallel by a scalar machin
origin sequenc the individu instruct
more other individu instruct
instruct in a particular data
hardwar depend interlock
class of instruct
a stream of scalar instruct

a compound instruct program
the compound of instruct for cisc architectur
text byte
system support for more difficult organ
some inform
partial refer point inform
multipl compound unit
modif of the instruct stream
instruct in a byte stream
compound capabl for ani number of instruct
capabl for architectur
architectur with other attribut
apparatu handle the worst case situat
a system with an apparatu
a parallel fashion on appropri instruct execut hardwar
a number of exampl

a compress unit
write back stage of the processor pipelin
thi circuitri
the reserv station and/or execut unit
the pipelin of a microprocessor
the instruct cach by the instruct align unit
the inform output
output signal from the decod
multi chip superscalar microprocessor modul
mid point
inform from the compress unit
decompress the inform
conveyanc of the inform
a second portion of the microprocessor function
a first portion of the function of the microprocessor
a decompress unit

a comput central process unit
valu for regist
the operand storag for regist file
the number of loop iter
the instruct that use those operand
storag of result
stack locat
simpler design
program visibl locat if the prior valu
program loop
output operand
operand in a comput system with sourc instruct identifi
normal locat for operand
newer valu
multipl loop depend operand
more loop
memori storag locat
loop iter execut
loop depend variabl
favor circumst multipl iter
direct forward of operand
avail area

a comput circuit
thereinto
the comput circuit
selector in a circuit
random access
output regist with data
logic mean
input data therethrough
data from an arbitrari regist
comput data
comput circuit with data

a comput control imag system
video display equip
these imag in each channel
the imag in accord with instruct from the field of view comput
the imag from all channel
the composit scene
special effect
sever aspect
raster scan format
plural channel
object into a buffer memori
multipl object pipelin display system
multipl object
more remot imag
digit form on mass storag devic
closer imag
cgsi
warp transform in order
the best result
row and/or column of object imag data
object imag data
compress ratio
cgsi pipelin perform improv
an order of rang from a viewer
a scene construct modul
a realist represent of a three dimension scene on a two dimension medium
a field of view comput

a comput element
token i
thi result in a cach memori
the result of anoth formula
the oper so the formula processor
the host for storag in a main memori
the formula processor convert pointer into valu
the formula processor
the formula from a host
subsequ token
retriev from the cach
result for the formula
result for a group of formula
resolut from the host microprocessor
identif
formula processor
depend inform
a subsequ formula
a sequenc of token
a result for a formula
a formula processor
a formula

a comput flow director
variou other equip
use of a single data interchang network
the variou unit
the variou comput unit
the use of plural data interchang network
the same data interchang network
the requir for the comput flow director
some data transmiss between variou comput unit
serial data transmiss
program digit comput unit
parallel data transmiss
other comput unit
multicomput system with simultan data interchang between comput
more data interchang network
mani other comput unit
mani comput unit
independ program
group of other comput unit
each comput unit
differ portion of a problem
data from a single other comput unit
conflict determin circuitri
comput unit
a plural of such comput unit
a multicomput system
a further embodi

a comput game
the tunabl unit
take on differ configur profil
such fine tune
more paramet of the function unit
differ portion of an applic program
differ applic program
configur profil
a spreadsheet
a second configur profil
a second applic program
a number of function unit
a first configur profil
a first applic program

a comput graphic
wx
v tangent
v deriv
the v depend of homogen coordin
the geometr coordin
the current view
the b spline function
success paramet point
parametr surfac evalu method
parametr surfac
paramet point
kv by nu
imag of the polygon
data in local memori and/or regist within the graphic
data from system memori
compon of the coordin
bottom v
bottom point
a v paramet
a control point stack

the three dimension object
each polygon processor

a comput imag gener system
visual scene for applic
the scene with pipelin
span detect
span
viewpoint onto a display
throughput of graphic data
the viewpoint on the object
the transfer of control
the span of the first such polygon
the span data
the geometri data a polygon
the exclus control of the memori control
the data for the next span
the current span onto a span of voxel
textur map space
textur for that span
span data
scene
three dimension object
viewpoint
triangle
z posit
triangle processor for 3-d graphic
thi input
the z posit of the polygon posit
the z posit of the pixel
the previou pixel descript
sever triangle processor
posit in the polygon
pixel from a scan line
output buffer
front of the z posit of the pixel
an x counter on the chip reder the pixel x posit
an associ materi valu
a triangle processor
a single semiconductor chip with input
a seri of triangle processor
a represent of a polygon
a portion of a three dimension object
the triangle list
the scene
the front face triangle
the back face triangle
the attribut for the front face triangle
the attribut for the back face triangle
scene on a display
scalar product of the triangle
normal vector with a vector from each respect triangle
list of like face coher primit
back face triangle
anoth array
an array of pointer
a seri of triangle list in an object data
a frame buffer control
retriev the color
procedur for that span
portion of memori for the graphic data
either display
effici render of three dimension scene
each such transfer
all such polygon
a textur map
a memori of a processor base system
a first such span
scene qualiti
realism of the comput
method of edg
geometri processor
fraction face area
each scene
display processor
consecut scene
a method for comput imag gener

a comput implement method
vector data processor
the vector bit stack
the proper state
the compil program
softwar code
prior state
element of the vector data processor
element at a point in time
effici stack util
ani other oper
an end
a vector data
a vector bit stack
a correct intermedi valu

a comput instruct execut unit
the slower instruct
the fast execut path
the averag instruct execut latenc
subsequ fast instruct
some embodi
slower instruct
faster instruct
fast instruct
differ execut path for differ categori of instruct
differ execut path
all execut path
a suffici number of clock cycl
a slower execut path
a fast execut path

transmiss packet
memori packet
list of memori packet
both memori
anoth memori packet
a plural of comput process

a comput network for high speed data commun
up stream transmiss
the transmiss
the start time
the signal convers system
the sc
the root
the comput network
synchron signal
synchron inform on a first frequenc band
synchron inform
second frequenc band for subsequ transmiss
sc on a second frequenc band
sc
other system
leaf node
high speed data commun modem
first frequenc band success receipt
first frequenc band
each client station
down stream data
data on a second frequenc band
client station on a second frequenc
a start time
a signal convers system
a leaf node
a data transmiss

a comput program
variou way
the preced of oper within the comput program
the latenc assumpt
the comput program
system of the latenc assumpt
object code compat process system
latenc assumpt inform
latenc assumpt
compat of the comput program

a comput readabl cmo ram memori devic
the non volatil memori
the content of the non volatil memori devic
the cmo ram devic
the cmo ram configur inform in the non volatil memori
system configur inform
method for cmo configur inform storag
flash into a cmo ram memori
flash
cmo ram configur inform
cmo configur inform in flash
block of the non volatil memori devic
a first block of memori
a copi of the cmo configur inform
a comput readabl ram memori devic
a comput readabl non volatil memori devic

a comput section
processor chip
other select paramet
no separ reconfigur time
intern reconfigur
extern reconfigur
configur under program control
configur by a set of multiplex
comput result
an extern random access memori
accord with configur inform

a comput system architectur
the result of execut of the instruct
the result field
the regist for the instruct
perform plural pipelin
perform in a counterflow pipelin processor
oper instruct
multipl instruct regist
multi issue/plur counterflow pipelin processor
individu one
each other in the pipelin
anoth approach
an opposit direct from stage
an operand field
a second sourc field for the operand
a second instruct regist
a group of sequenti stage
a first sourc field for the operand
a first instruct regist
a first direct from stage

a comput system share memori between multipl processor
the subsect level of the memori
the section of memori
the processor level
the memori path
the memori into a plural of section
subsect in the memori
regist in each subsect of memori
refer the same section
refer the same bank of memori
refer conflict resolut
each section of memori
conflict between port in the processor
conflict between differ processor
a subsect at a time
a memori path between each processor

a comput with a condit code regist file
the plural of the condit code regist
the condit set instruct
the condit code valu
the condit code regist file
primari express
multipl condit code regist
condit set instruct that each produc a condit code valu for storag
condit code address field of the instruct
condit branch instruct that branch
comput with instruct that use an address field
analysi of a condit code valu
a plural of address condit code regist
a direct address field
a condit code valu

a comput with cach memori
use with program
the order of memori refer code in the program
the gener of such cach
the complet of memori access
compil method

a concurr process system
the target devic
the process code
the complet data transact
multipl instruct multipl data comput system
multipl instruct multipl data
great flexibl in util of system resourc
each transact on the bu 5
data valid
control regist in the interfac
complet transact code
addit clock period
acknowledg of receipt
a process code
a data pipelin system

a condit break instruct
repcc
instruct with a minimum number of instruct cycl
brkcc
a repeat instruct
a loop count within a loop counter
a loop count
a condit repeat instruct
a condit do loop instruct

a condit carri adder
techniqu for digit processor
small set of cell
organ of the cell
n digit operand
mo techniqu
low circuit complex in lsi by either bipolar
ani length adder with both high absolut perform
an incrementor

a condit code field
the specif data
the program control unit output an instruct address
the instruct word in the program memori
the current data
the current condit code flag in accord with the condit code field
the condit code field
method for condit data oper with no condit code updat
decod circuitri
condit code regist
condit code decod circuitri
an instruct word
a sequenc of instruct word
a current condit code flag
a condit code regist

a condit code mask field in instruct
use by other instruct
those condit code bit
the set of a condit
the point of instruct complet
the latenc from condit code gener
the decis
the condit decis from the point of instruct issue
the branch umbra
stale condit code
mani instruct
independ instruct sequenc
condit instruct execut issue
condit instruct execut
condit code reserv station
condit code flag
comput processor with an effici mean
code use

a condit discrimin
the micro address analyz circuit
the branch readi inform of the first micro instruct i
the actual execut of the branch request in accord with the result of the condit discrimin
prefetch a target branch
pipelin processor with prefetch circuit
nonform of a condit branch micro instruct result
memori befor the micro rom output
a micro rom address decod
a micro address gener circuit
a micro address analyz circuit
a macro instruct i

a condit jump instruct
transfer path
the valu of the flag regist
the loop control unit
pipelin processor with hardwar loop function
other processing
instruct address stack
content of program counter
a valu of a flag regist
a loop escap oper
a loop control unit
a hardwar loop function

a condit microbranch instruct
uniqu microinstruct
the select of the next sequenti microinstruct address
the outcom of the execut of the condit microbranch instruct by the execut unit
the no op/prefetch apparatu permit either the next sequenti microinstruct address
the no op address
the nanostor
the microstor
the instruct execut system
the execut of the no op microinstruct in the execut unit
the execut of the condit branch microinstruct by the execut unit
the execut of a microbranch instruct
the condit microbranch instruct
sequenc of microinstruct address
resolut of the pipelin
instruct execut system
excess delay
cycl of delay
anoth non sequenti microinstruct address
anoth non sequenti microinstruct
addit real estat
a no op/prefetch apparatu
a no op microinstruct
a no op address into the nanostor
a nanostor
a microstor
a microinstruct address

a condit move instruct
use of previous establish data structur
the sequenti of the instruct stream
the provis
the implement of atom byte
the facil
store/condit instruct
short branche
regist to regist oper
non align load
memori access data width
mani short branche
load/stor oper
instruct size
in regist byte extract
byte manipul instruct
byte compar oper for high perform processor
a third if the condit
a high perform cpu of the risc

a condit move processor
the stream of data
the necessari oper on the data element
smaller circuit area
rom like pla
residu
the residu number
the residu input number
the redund residu digit
the plural of oalu
the inform processor at the same time
the inform processor
modular subtract
modular multipl
each digit of the residu number
base number
base extens processor
base convert
an addit channel of oalu
a residu number a an input
a redund residu digit
method for video
iter fashion
an mpeg-2 decod circuit

a condit program flow control instruct
the program flow control instruct
the execut unit of the invent
the condit program flow control instruct
the candid instruct if the condit program flow control instruct
the candid instruct
resolut of the condit program flow control instruct in respons
processor microarchitectur for effici process of instruct in a program
number of instruct from the condit program flow control instruct
more candid instruct in the buffer
more candid instruct between the target instruct
instruct in the program from the memori
control logic store
a program flow control instruct
a processor microarchitectur for effici process of instruct in a program
a mispredict penalti

a condit that each data
the order of receipt of the set of data signal
the data bank
the bank order
the arriv number
respect storag locat
respect data signal within respect data bank
respect data signal
respect data bank
each other i
differ data bank
data storag devic
bank order
a time befor complet of the write
a plural of data band

the transmiss characterist of the pipe
the remot unit
the proxim
the locat of the leak
the exist
the amplitud
the acoust signal of a leak from ambient acoust signal
addit equip
acoust signal from the pipe
acoust featur of the acoust signal
a plural of remot acoust transmiss sensor unit
a particular remot unit

a conduct gener
valu from the ground
the pseudo kp
the pcp valu
the occurr of magnet storm
the ground
the geomagnet paramet from the conduct valu
the geomagnet forecast system
the electr field valu
substorm
space weather data
space weather
space base measur
solar wind veloc data
method forecast geomagnet paramet
method forecast geomagnet event
ionospher forecast
interplanetari magnet field data
ground
underground pipe
locat of a leak in a vessel
detect of leak in vessel
a contain
electr field pattern from the pseudo kp valu
effect on ionospher current
current from ground
conduct valu from the ground
au valu
au predict gener
an electr field pattern gener
an al
an adapt feedback gener
al
a second predict gener
a pseudo kp valu gener
a pseudo kp
a polar cap
a midnight equatori boundari
a first predict gener

a cone of normal
view
the patch level befor tessel into triangle
thi cone
these volum
the same cone of normal
the normal function of the patch
the direct of the normal of the normal function
the creation time of the patch
the convex hull properti of the patch
the cone axi
substanti time saving
subsequ view of the same patch
quick patch level test in a time manner
patch
parallel plane
inform about the patch
cone
the patch
the part sens signal
unaccept part from the path of conveyanc
typic featur
the vision station
the transport
the oper of the group of processor
the inspect task
the group of processor
the allow deviat of the featur
the activ camera
signal for use by an actuat
refer data
part height
part featur
own group
outer diamet
multipl scene
model data
machin vision
limit data
lamp
featur detect algorithm
featur accept signal
each group of processor
concentr
camera
a single optic setup at a vision station
a particular view of the part
a larg varieti of part
a coordin processor

a configur
accord with anoth embodi of the invent

a configur signal repres of configur of the vector calcul unit in each processor
vector calcul unit
the vector calcul unit in the other processor
the vector calcul
multiprocessor system with vector pipelin
an access control unit control access oper of the processor on the basi of the configur signal in the processor
a vector calcul

a conflict between success instruct
the plural of address data
the output of the address adder
the main memori in an operand
the execut result data
the address of the second operand
instruct under execut
instruct after the first operand
first operand
execut result data
an operand address calcul stage
an address adder
address conflict instruct
a to be execut succeed instruct
a sum of the plural of address data
a plural of address data
a first operand from a main memori

a conflict detect unit
thi sourc data
the termin of execut
the sourc data of the present instruct
the sourc data by pass unit
the establish of the sourc data of the present instruct
system for by pass control in pipelin oper of comput
a system for comput pipelin oper
a sourc data by pass unit
a data establish indic unit

a conflict map field
the conflict map field
the address field
row of entri
resolut in a multi port non block cach
parallel at the multi port non block cach
intra row conflict between entri
in line bank conflict detect
group of non conflict entri
bit in the conflict map field
an address of the access request
an address field
a picker
a multi port non block cach
a data access request from a lower level devic in the processor

n processor
p processor
own memori
order a 
n instruct
more input high level languag
interpret digit data processor
instruct at the level
a multi level hierarchi of processor
a hierarch interpret of each input high level languag

a conflict resolut
the self rout crossbar switch the request
the same output port of the self rout crossbar switch at the same time
the output of the align
the n processor
the memori modul
the conflict resolut logic
the align input the request
the activ request
sever memori bank
serial
system for perform
serial of the pipelin
perform monitor counter
number of addit cycl
mode control regist
length of time of execut of serial instruct in a pipelin
length of time of execut of serial instruct
least pmc
identif of frequenc
configur the oper
a number of addit cycl
a loss of effici
router
port content
no port content
no bank content
n memori modul
multi memori system
each output port
each output
each input port
crossbar switch
bank content through the use of align
bank content
a self rout crossbar switch interconnect a plural of processor with a plural of memori modul
a self rout crossbar switch
a new request
a consecut fashion

a conflict resolut system
the sequenc of memori request
the cross connect switche
the conflict resolut system
the address bellow
multipl parallel memori request
multipl memori bank
multipl independ memori oper per cycl
memori system with multipl parallel access
memori in processor
cross connect switche
conflict resolut
an address bellow
a control logic block

such processor
thi way the processor
the variou process level
the control instruct
the arithmet control
such process level by the arithmet control
such data a both data
such data
such control level
such control instruct
pipelin signal processor
control instruct pass through the processor
accord with a control instruct
a programm arithmet control
a prior process
a pipelin arithmet unit
a new process

a connect
the thread slot
the number of the instruct stream
the exchang control
the context of the instruct stream
the context backup memori
the connect between the instruct prepar unit
result of the thread
n thread slot
multistream instruct processor
m instruct execut unit
instruct in accord
instruct from n instruct stream
fetches/decod instruct from the instruct stream
far execut of the instruct stream
aninstructionpreparationunit
an instruct stream control
an execut connect unit
an exchang control
a wait state for an instruct stream
a multistream instruct processor
a context of the instruct stream
a context backup memori

a connect between discontinu pipe stage in the core
use with a wide varieti of instruct
the use of a pipe stage
the core bundle all control
the bundle
synchron concern
downstream pipelin oper with an instruct address in a first stage
an unknown depth with a single microprocessor core
an instruct pointer gener stage
an extern pipe stage
address inform in a single bundle that travers the extern pipe stage a a group
a plural of pipe stage

a connect for a control memori
suitabl selector
programm processor for word wise digit signal process
a multipli element
a doubl bu

a connect valu
use in the network upon detect of a faulti compon
thi subset
thi set of avail comput node
the set of avail comput node
the largest set
node within the network
node in the system
node in the subset
each other comput node in the subset
a subset

a connectionless
tupl
the plural of comput
the execut of parallel program
multicomput system
multicomput architectur
method for automat sequenti to parallel program partit
exclus read oper
determinist delay
coars grain simd
backbon failur

a consecut sequenc
circular carri lookahead
circular carri

a consist interfac
the local system bu support
the cpu subsystem
peripher subsystem
open
multipl microprocessor
microcomput system
burst transact
an open high speed local system

a constant ga volum flow rate through a venturi scrubber
seri with the fan
power level
ga clean apparatu
draft fan
constant pressur drop across the venturi scrubber
a ga clean apparatu

temperatur
pressur

a constant pressur cylind
voltag signal
the switch array
the statu of hydraul valv position the liquid level
the posit transmitt
the posit of the excit
the posit of object
storag vessel
solid state compon
proxim
precis
practic variat of the physicoelectr proxim switch array
posit transmitt
no contact between the physic excit
movement
some function
visibl discontinu
the touch tablet
the read of pixel for display a an imag on a monitor
the processor 22
the other data
the framestor
stylu pressur
signific chang in stylu pressur
pressur of a line
pixel from the framestor
other chang
numer valu
larg chang in scale
imag pixel
featur of the system
electron graphic system
colour shape
batche
an input of the brush processor
an electron graphic system
a user on a touch tablet
a pipelin brush processor
a framestor
moder resolut
ma
liquid
less power
inch
hundred of feet
gaseou materi from pipelin
further circuit
excel accuraci
digit output
differenti pressur
chemic hazard
array of physicoelectr proxim switche
a string of puls
a physic excit
a digit posit transmitt

dilat
digit imag

a constant valu
transform of an imag
serial imag on a word by word basi
grayscal imag transform
eros transform in grayscal imag

a construct
vector comput and/or cell
vector comput
the effici of mimd
parallel digit process system
output buse in place of data
optic signal
optic interconnect between control section
multi bit inform
logic comput
light beam
control signal input buse
chip in the form of optic signal
chip for wide applic
buse between processor
and/or a larg number of cell
a larg number of cell

a content
the regist frame
the load/stor line
regist frame load/stor line
bundle
unit further i
the type of control flow instruct
predecod data
no branch mispredict
multipl type of control flow instruct
multipl control flow instruct
mechan with simultan predict of control flow instruct
bundle address
branch predict data
an uncondit branch
a sequenti address
a return address from the return address stack
a thread sequenti start instruct
a thread return instruct
a thread parallel start instruct
a thread end instruct
a sequenti execut of thread
a regist frame
a plural of regist bank
a parallel execut

the document
the second portion of the document
the first portion of the document
second portion of a document
inform from the electr signal by the mean
data buffer
camera assembli
both pipe
an imag of the inform
an imag digit
an electr signal in respons
a transposer/compressor
a resequenc
a first pipe

a content index i
the term
the search criteria
the queri
the content index search system
the content index i
the collect of object
search result refer
search result correct routin
new object
date with respect
collect of object
an initi search result in respons
accur search result
a queri on a collect of object
a corpu of document
a content index search system

a content of the debug except
the success of the condit
the result of the determin of the condit
the result of the actual determin
the exist of the execut of the debug
the execut of the debug routin i
instruct in a pipelin process
decod a condit branch instruct
branch instrument
a debug except produc flag

a context switch
variou categori of instruct
map a rang of physic address bit into a first section of the operand cach storag
a time share basi
a one to one basi

a context switch occur
the time share basi
an instruct cach haivng variou categori of instruct
a one to one basi map a rang of physic address bit into a first section of the operand cach storag

a contigu prefetch buffer
x86 processor
thi field
the target of a short branch
the target of a branch
the same prefetch buffer a the branch
the locat of the target instruct for a short branch within a prefetch block
the exemplari prefetch unit
target locat inform in a branch target cach
short branche in a prefetch buffer
previou prefetch block
prefetch request in the case of short branche
prefetch block locat field
instruct byte for the target instruct
each entri store
content for cach access
bu traffic
a three block prefetch buffer
a prefetch request for the prefetch block
a prefetch block of instruct byte
a prefetch block locat

a continu display
thi imag a an inset window on a video monitor display
the vertic rate of the input signal i
the vertic rate of the display
the updat buffer copi
the top line of the input window
the start of the activ portion of the input frame at a vertic posit
the pipelin dual memori system
the input imag
the copi oper
no interact between input
entir content into the display buffer everi time the input signal
display of raster scan imageri signal in relocat window on a video monitor
display buffer
copi
use in a fault toler system
the previou execut of a command by the processor
the index regist
the event origin copi of the index regist
the event of a rollback
origin copi of the index regist
copi of origin index regist
a method for the select of origin data from a regist log
a frame updat
a digit raster scan imag from an extern sourc

a continu process for select countercurr extract
extract process
convers of lean oil absorpt process

a continu queue an indic
the messag from a messag queue
the continu

a continu refer clock
the delay of the extern delay circuit
the delay lock loop
the continu refer clock
signal from the variabl voltag circuit
output clock
delay of the extern delay circuit
delay lock loop
clock signal from the delay lock loop
a variabl delay circuit
a discontinu refer clock
a delay lock loop
a control voltag output from the delay lock loop

a continu sequenc of clock puls
the simd microprocessor
the rrc
the plural of simd microprocessor
the instruct into a seri of comput
the extern host comput
the comput on the data by procedur call
structur interconnect the plural of simd microprocessor
special purpos parallel comput architectur for real time control
simul in robot applic
parallel in each oper
matrix vector oper in parallel
instruct between the simd microprocessor
fine grain parallel
each simd processor
data among the simd microprocessor
answer
an simd parallel processor
an simd architectur
an mimd simd parallel architectur
an mimd architectur
an extern host comput
activ of the simd microprocessor
a system bu
a real time robot control
a plural of simd microprocessor
a path for the flow of data
a high degree of parallel in comput for robot

a continu stream of digit data
time of the slowest element
the frequenc domain
the adapt processor
multi channel adapt cancel
more section
loss of cancel
concurr weight adjust
and/or the number of refer tap
an adapt cancel
adapt cancel

a control board
the time of input/output of the data between the main memori
the time of input/output of the data between the buffer memori
the processor through output data buse
the oper sequenc of the processor
the input/output buse
the form of a pipe line
second control
pipe line data processor system of synchron type
memori devic with buffer memori
input/output data
input data buse
first control
data from the processor
a pipe line data processor system

a control code
unit in accord with the control code
the regist number in an instruct
the regist number from a memori area
the regist list by an prioriti encod
system for pipelin
result of an oper code field
plural data between the memori
multi function instruct
instruct execut control unit
data into the memori area from the regist
binari digit
access a memori
a regist list field

a control command
variou class of instruct
the wide varieti of integ
the result queue
the respect function unit
the microcod execut unit
the class of instruct
respect function unit
control of multipl function unit with parallel oper
accord with the entri
a tag in the entri at the head of the queue
a result queue
a new oper

a control comput
time sampl signal
the system control comput
the statu of the oper
the process portion of the data packet
the monitor field of ani data packet
the monitor field
the health of each dsp
the dsp monitor the control field for command
the data packet
the data channel
specif dsp
real time process
output format
dsp per stage
dsp of the next stage
dsp of the last stage
append a control field
an arrang of output data channel
a real time data
a pre process arrang of data channel
a monitor field
a front end dsp

a control data gener for a sort processor
pipelin merg sorter with run length
inform about the length of input data
each sort processor between the first function
a control data output unit
a control data gener unit

a control for a simd processor array
the stage of the control
the routin sequenc
the array element
stage hierarch control
routin librari
instruct at the function
if/then/els
flow control oper
feedback of progress
do/whil
control for a simd/mimd array
command execut progress
a steadi flow of command

a control for the edg
use with avion display system
the raster engin control
the raster engin
the memori interfac compon
the line interpol
the edg interpol
the bit map memori control
the bit map memori
raster graphic for video gener
parallel polygon/pixel
line interpol
interpret unit
interpol control
gener interpol polygon processor interfac
engin for a digit map
digit map display
data from the raster engin control
data from the plural of output
data from the memori interfac
data from the instruct interfac unit
data from the edg interpol
control signal from a bit
an output of the first edg pipelin
an output of the edg interpol
an output from the second stage of the edg pipelin
an imag scanner
an edg interpol
a second output of the raster engin control
a second edg pipelin
a raster engin control
a raster engin
a plural of output from the line interpol
a parallel polygon/pixel
a line interpol
a first edg pipelin

a control line
two bit counter
thi branch
the next state valu
the manner
the load of the c regist
the direct of a plural of branche
the correl base branch histori
tent branch histori inform for the branch
tent branch histori inform
such processor event
processor event
inform from the instruct decod
hit/miss inform from a branch predict cach
hardwar in respons
hardwar control
configur branch predict for a processor
chang in the instruct workload
branch predict hardwar
branch histori inform
a third aspect of the invent
a second aspect of the invent
a miss in the bpc
a fourth aspect of the invent
a first aspect of the invent
a correl base branch histori

a control memori
the control memori

an agent
the request on the bu
the memori unit retriev thi cach line
the event of a read request
the entir cach line over the bu
the cach line in main memori
retriev the cach line data
invalid oper
each agent on the bu snoop
data over the bu
cach consist
anoth agent
agent transfer

a control method mixe request and repli packet on the bu
the use of a next bu cycl
the state of a grant queue
the pipelin queue
the next avail bu cycl upon the condit that the pipelin queue
the next avail bu cycl upon the condit that the grant queue
the highest prioriti slot
the great queue
the bandwidth of a packet
specif line
request preced
request packet that request data from an agent
packet that return data
own slot in the pipelin queue until a later time
a transact in slot 2 of the pipelin queue
a request packet
a pipe queue in accord

a control modul
the volum of fluid in the system
the return portion
the pipe network
the fluid with system
the flow of the fluid through the system in a manner
second pressur sourc
fluid flow through the pipe network
each tank
control modul
continu recircul fluid deliveri system
bumpless flow of the fluid
a vent line
a third tank
a second tank
a return portion
a pressur sourc
a pressur
a pipelin network
a multipl of valv
a fluid deliveri system
a first tank

a control panel
valv for select introduct of hydraul fluid medium into the magazin
the pig into the pipelin
the pig for pig
the magazin behind the free piston for movement of the free piston
the ga transmiss pipelin under the control of a timer
pipelin pig
pig
mechan after each pig
liquid pump
a tubular magazin
a sourc of hydraul fluid medium
a plural of pipelin pig in serial manner into a ga transmiss pipelin
a plural of pig
a horizont pipelin pig
a free piston

a control portion
the transfer of the data from memori entri
the plural of valu
the control portion of memori entri
each edg interfac circuit
bu protocol simul in a multi processor data
bu protocol simul
a second bu protocol
a first bu protocol

a control processor of the system
the third memori locat c
the system for respect one
the pair of memori locat
respect third memori locat c
memori locat of a plural of pair of memori locat
event in the system
each pair of memori locat
data in the third memori locat c
data from the pair of memori locat
b of the system in depend upon the event

a control program
vacant decod
the logic sequenc of the instruct
the logic sequenc
the hierarchi
the decod unit
the decod buffer
instruct in a logic sequenc
higher signific avail vacant decod unit
each decod unit
an instruct buffer of fifo construct
an apparatu for use
a number of decod unit
a highest signific decod unit in order
a hierarch manner from a lowest signific decod unit
a fifo construct
a decod buffer

a control program memori
these arithmet oper
the process of control
the persent invent
the parallel port
the interfac unit transfer
the interfac unit
the extern interfac unit
the control program
the arithmet element control
the amount of hardward
signal process function
point arithmet oper on the data
pair of port
microprogram instruct
matrix signal process algorithm
load applic program into the control program memori
individu port
individu parallel port
form a port
each arithmet element
data signal in the signal processor
data signal from extern signal sourc
data signal between the signal processor
arithmet logic unit in order
an extern interfac unit
an arithmet element control
accord with applic program
a split
a serial control port
a plural of data format
a plural of bidirect parallel port
a plural of bidirect configur parallel port
a high perform architectur for use with vector

a control regist execut log
the test regist
the diagnost circuitri
the content of the log
test regist
log pointer
log address
diagnost circuitri in a data processor
diagnost circuitri for use with the processor of a data
control store address from a control regist
control store address
a log pointer
a control store address for comparison with control store address

a control rom
the time the micro instruct
the control rom
specif operand
regist specif operand
regist gener micro instruct within an instruct queue
method for regist
gener operand
gener micro instruct within a pipelin processor
execut by later stage in the pipelin
delay in the pipelin
a rom instruct queue
a micro instruct
a hole

a control section
the statist calcul section
statist processor
desir statist result on the basi of data
data everi time
a statist processor
a statist process on the basi
a statist calcul section

the control storag
control storag

a control storag
the instruct data into the control storag while the part of the pipelin
the error in the read instruct data
the detect of an error
error recoveri system in a data processor
detect code
an error recoveri system in a data processor of the pipelin type
an error correct circuit
an error correct
a part of pipelin
a pariti check circuit check instruct

a control store rom
two dimension data array
the use of the multiplex
the sum of the address from the multiplex
the sequenc regist
the output of thi multiplex
the output of the multiplex
the output of the base regist
the microprocessor under microprogram control in high through put real time applic
the microprocessor data loop
the micro operand ram
the flexibl address
system for operand memori
microinstruct regist
micro operand storag
micro address regist
loop string
local storag of data
control store
both microinstruct word
base regist
a sequenc regist
a pipelin for output control store microinstruct
a microprocessor comput
a microinstruct in the control store

a control subsystem
the other element of the microprocessor in respons
the instruct in the instruct stream
the inform retriev subsystem
the inform retriev oper
the control subsystem
sourc regist
regist a a sourc regist
load instruct in accord
instruct of a plural of instruct type
inform storag subsystem for storag in a regist
inform input
fault flag
fault condit in respons
fault condit
detect of a fault condit
an instruct stream
an instruct in the instruct stream of the inform retriev type
an instruct in the instruct stream of anoth type
an inform retriev subsystem
an inform retriev oper
an inform retriev instruct type
access fault indicia
a microprocessor in a comput system

the first data
the second data
a first data

a control system emul a multi task environ
the upstream most instanti of a task obtain data from a data sourc
the upstream most instanti
the task from the task librari
ripple
the upstream most instanti of a task obtain a scan line from an imag data sourc
the task from the librari
the memori alloc
the host applic in the second channel
the host applic
system for a single applic environ
a host applic
instanti
the heater of the imag
the first channel
scanlin of imag data
imag header
imag from an imag sourc
emul a multi task environ
each instanti of a task from the task librari
a first channel
multi task pipelin
each instanti of a task from the task librari further oper on the data
data from a data sourc
a task librari
a downstream most section of the pipelin

a control unit for a function processor
the transfer control
the microprogram store
scratch pad storag element
oper of memori transfer
memori address stack
loop control paramet
long sequenc of signal process subroutin without extern control
level memori system
flexibl respons
flexibl in program task changeov
either main memori address
control unit for a function processor
control oper with storag
control branch stack
common page
coeffici memori address
coeffici address stack
buffer oper
an addit featur
address increment
a plural of scratch pad buffer in the arithmet unit in a synchron manner
a plural of main memori modul
a dual clock arrang

a second storag
a first storag

a control word read from the first storag
the second storag
the error recoveri system
the error in the control word
the comput system process instruct in a sequenc
second storag
flow
thi prior art arrang
the second execut unit
the same direct a a first execut unit
the oper data
the main pipelin
the arrang of thi invent
suffici time
subsequ process until all oper data
specif oper
high speed multipl oper
devic for instruct execut
an earli stage of pipelin
a second execut unit
a later stage
error recoveri system
each flow
each cycl of each flow
cycl of a flow
control word by the comput system
control store in a comput system
an instruct control word
an error recoveri system
an error recoveri
an error in the control word read from the first storag
an error in a control word for an instruct
a sequenc of cycl
a pipelin architectur type comput system

a control/regist unit
the princip process unit
multipl special purpos
concurr vector signal processor
a vector signal processor
a vector buffer unit
a data movement unit

a control/statu regist
unit through a regist
transfer data from the control/statu regist
the slave circuitri
the master circuitri request host bu oper
the master circuitri
the control store a a mailbox for commun with the host processor
slave circuitri
single word
simd architectur for connect
request for data
request for coprocessor oper from the host processor
other host bu master
multi word dma
master circuitri
data in the control/statu regist
data in horizont format so that corner
data between the host
data between the coprocessor
a pipelin of regist

a conveni method
video data stream
the video pipe
the media devic
the local area network control for the interprocessor commun
resid on the media devic microprocessor control board
physic assign of the devic commun on the pipelin
multipl media devic
media devic
media control
local microprocessor
instruct for the pipelin switch interconnect through the interprocessor serial commun
differ configur in respons
connect option
circuit card
audio input
audio devic
a softwar driver interconnect the multipl video
a pair of analog multiplex
a number of port
a multi channel bi direct video
a motherboard
a media devic
a digit interprocessor commun

a convent binari memori
the non null memori
the non null data signal
the non null address signal
null wavefront
null convent interfac circuit
null convent data signal
null convent address signal
non null data signal in respons
non null convent memori
non null address signal
circuit control data
an interfac circuit between null convent logic
a second convers circuit
a non null convent memori circuit
a first convers circuit

the storag locat
a storag locat

a convent manner
these item
the primit code
the pixel code in an imag memori
the new pixel code
the higher prioriti
the convers from primit graphic
symbol code into an array of pixel
raster graphic engin
prioriti in the pixel code
primit graphic
primit code
pixel code in the storag locat
movement of graphic
item in high level graphic
individu pixel code
graphic on a display
a symbol font memori
a new pixel code
a display prioriti of the new pixel code

a convent parallel processor
time the amount
these parallel processor
number of individu processor
n number of individu processor
equival
data of differ length
data of a length of n
data of a length
a single parallel processor
a serial connect of a first parallel processor
a second parallel processor
a good effici on signal

a convent processor driven instruct path
the processor driven mode of oper
the probe mode
the extern command mode
sever selector
no implicit updat
multipl pipelin processor
microprocessor with an extern command mode for diagnosi
i/o space
direct access
boundari scan
an instruct in the probe model
an extern pin
an extern instruct path
an extern command mode
an extern command
an altern memori
accord with the ieee
a debug except
a convent test access port

a convent store
the vector control unit decod the vector instruct
oper function in the fastest possibl manner
logic unit within the vector
execut of the first microinstruct
an entri microword from a store for the immedi execut of the first microinstruct within a sequenc of microinstruct
a logic cach through a sourc
a further aspect of the comput

a converg of the cordic algorithm despit an ambigu region in the sign detect of carri save number
vector rotat in carri save architectur
vector rotat
the low chip surfac requir
the iter stage
the final result vector
the extrem high process
the cordic processor on separ line path
the carri save architectur
simpli construct base cell of the vector
problem in real time process
other circuit compon
intermedi result in the form of carri
incomplet addition/subtract oper
exampl a multipli
coordin rotat digit comput processor
carri save architectur in connect
angle iter stage
an adder at the processor output
a result of the carri save architectur
a plural of vector iter stage
a plural of angle iter stage
a high regular of the overal structur
a cordic processor

the valu of the window start pointer regist
point regist number in the instruct

a convers circuit
thi end
the window start pointer valid regist
the regist field
the convers circuit
post store instruct
point regist than the number of regist
point regist number on the basi of the valu of the window start pointer regist
length from the ordinari instruct
high speed execut of a program
an ordinari instruct
a window start pointer valid regist
a window start pointer regist
a valu at the window start pointer regist
a regist field
a greater number of regist than regist
a convers pattern

a converter/round
the subtract necessri
the remaind of the multipli circuitri
the next estim
the multipli array
the final approxim with an operand
the correct gener
the converter/round
squar root function
point/integ processor with divid
parallel with other multipl
a subtract of the product output form the multipli array
a multipli array
a correct gener

a convolut portion
time cycl
the least mean squar algorithm
the least mean squar
convolut oper
both portion for concurr use
an updat portion
an n tap filter with a minimum amount of circuiti
algorithm in an n tap digit filter
a filter structur
a filter processor

a copi of physic address
the shadow tlb
the primari tlb
shadow translat look asid buffer
logic address into physic address
a shadow tlb
a primari translat look asid buffer
a physic address cach

a copi of the cach directori
the scu cach directori in order
the processor cach
the presenc
the main memori in a multi processor system
the main memori in a multi processor comput system
the data inconsist state
the data inconsist
the data in main memori
the cach of some processor
the abov describ data inconsist state
main memori by a system unit
kind of data inconsist
fix up sequenc
data inconsist state
data inconsist
data in the cach
data consist between a plural of individu processor cach memori
data consist between a plural of cach memori
consist manner
a scu base multi process system
a request for a oper from a system unit
a data transact request

a copi of the cach memori address tag store
use the memori manag circuit
the ccu access the memori modul
the ccu
the address translat circuit
share a common control unit
ccu
an address translat circuit
a write through cach memori
a secondari storag facil
a multiprocessor data
a memori manag circuit

the shifter
a shifter

a copi of the counter
the proper number of iter
the maximum number of iter
the last flow of an iter
the iter in the pipelin
the current valu of the counter variabl i
the current iter
the counter variabl i
stage near the end of the pipelin
short string
pipelin flow
pipelin capac
iter
the solut
the input of the multipli via the bu
the aforesaid bu via a switch
squar root extract function by approxim
squar root extract
larg scale calcul
bit width
a reduct
a greater bit width
dispatch after comparis
decrement the counter
compar of a charact in the string
an iter a number of time

a copi of the data
the present invent associ state with line
the plural of line state
the data in the cach line
the agent in the system
the agent
state transit
stale data
result in a cach miss
no agent
multipl level of cach
multilevel cach hierarchi coher in a multiprocessor comput system
memori and/or multipl activ agent
memori across a system
memori access request in accord with a protocol
data consist
ani other copi
agent with a cach hierarchi
agent in m state
activ by other bu agent
a present state
a plural of line state
a line of a cach
a line in e state
a line in  state
a copi of the data in a line of the cach

a copi of the first few byte of the second instruct
variabl length instruct in a superscalar processor
third instruct
the secondari buffer
the previou cycl thi secondari instruct buffer
the previou cycl
the length of the second instruct
the initi cycl after a reset
the first byte of the third instruct
the first byte of the fourth instruct
the byte from the fourth instruct
that second instruct
that previou cycl
second instruct proceed without delay
length decod
instruct per clock cycl
instruct byte in a larg instruct buffer
byte of the second instruct
a secondari instruct buffer
a copi of the first instruct

the time slot for use of the cach
the time slot for data transfer

a copi of the tag store in the cach
these transact
the cach tag
the cach for an updat
duplic tag store
an accur indic of the content of the cach
a second cach access in order
a second access
a queue with order

a coprocessor system
the fpu upon receipt
the execut of the current command
the discrimin result
the current command
oper in a processor system
each other through buse
criterion
command after the complet of execut of the current command
advanc on the basi of a time
a short command
a long command
a float point process unit
a current command

a copyback buffer
the victim line
the stack rel memori access access the second of the pair of cach
the stack rel memori access
the second of the pair of cach
the second cach
the pair of cach for storag
the pair of cach
the first cach
the copyback
stage of the instruct
stack rel memori access
differ stage of an instruct
data between a pair of cach
a victim line for replac
a victim line copyback

a cordic algorithm unit for rapid vector rotat
trigonometr function calcul
three dimension vector processor
sever level within the processor
regist to regist data
real time invers kinemat
rapid vector calcul
program oper flexibl
operand between regist file
invers dynam calcul
execut unit architectur
broadcast buffer
a three wide regist
a robot control processor

a core set of graphic modul
video insert
the vip architectur with the capabl
the vip architectur
the video insert process system
the use of independ graphic path
the system capabl
the system architect
the graphic system with the capabl of imag overlay
the final imag
the differ graphic path on a pixel by pixel basi without degrad of overal system perform
shape
the test imag
the method of the invent
the inspect class
that instanti an inspect object from an inspect class
result of those inspect
more test imag
characterist of the featur
angular orient
a type of the featur
a test object from a test class
a method member of that test object
a method member of that object
a machin vision system of the type that inspect a featur
a machin vision inspect system
real time respons requir
parallel approach
n time for each set of graphic path
multipl imag
independ graphic path
imag from multipl frame buffer into a single display imag
graphic process
each pixel sourc
a wide rang of graphic process requir

a corner node
the mesh
self time mesh
form a self time pipelin with each individu messag
each processor node
dimension mesh of processor node
dimension mesh of messag
chip with data
a self time messag
a messag within that particular messag
a messag within individu messag
a matrix of node

a corner turn memori array
the row direct of the input section
the first pair of memori cell
the column direct of the input section
space effici
readout section
parallel to serial convers devic
parallel to serial convers
linear transform devic
data into a first pair of memori cell
data from a second pair of memori cell
corner turn memori
an input section of the devic
a parallel to serial convers devic

a correct error
transit of the correct error
the second data stream
the first data stream
the correct error
system output the first data stream
data processor oper
code protocol
a second data stream
a first data stream in a data

a correct factor
thick
the thick
the second apparatu
the permeabl
the mathemat squar root of the permeabl
the magnitud of the insid diamet
permeabl
first apparatu
electromagnet inspect tool for ferromagnet casing
diamet
an electromagnet thick tool
a second apparatu
a permeabl signal repres of the permeabl

a correct oper result
the respect instruct execut unit
the instruct execut unit on the basi
the increas in the oper unit
the distribut circuit
the control of an instruct execut unit
inform of that instruct
enhanc
data processor with parallel oper oper unit
anoth while
a plural of instruct execut unit

a correct predict rate
the subroutin call instruct in a stack type structur
the return stack
the return instruct
the esp regist valu
the correct predict rate in the absenc of fake return instruct
the correct predict address for thi return instruct
superscalar microprocessor stack structur
subroutin return address
subroutin call instruct
fake return instruct
esp valu
esp
clock cycl that a return instruct
an inequ
an indic of the return instruct detect
an esp regist valu
a return stack

a correl of a model
the cach memori array in accord with imag pixel valu
fast correl
an array of algebra squar of pixel valu

a correspond
user defin oper code
the result regist
the program circuitri
the pipelin oper code
the logic circuitri within the pipelin stage
result latch circuitri
program circuitri
plural pipelin stage
pipelin direct
logic oper on the result data in accord with a pipelin oper code
issue data
instruct latch circuitri
instruct in the first pipelin direct
execut of the pipelin oper code
counterflow pipelin processor architectur for semi custom applic specif ic
certain pipelin stage
branch predict capabl
an instruct flow in a first direct
a result regist store
a correspond between a user defin oper code

a count
the volum
spatial characterist
object in an imag
more height of portion of the object
height with a count
characterist of three dimension object
a volum of the object
a cross section area of the object at that height with a count
a cross section area of the object abov that height
a cross section area of an object
a count of pixel in the object

a count of a number of resourc
the number of resourc
the instruct metadata
pipelin resourc of a processor
pipelin resourc in a superscalar processor
instruct with instruct metadata
instruct in the execut pipelin
a number of pipelin resourc

the operand data
the second associ memori
the first associ memori the instruct control unit
the first associ memori
an instruct from the first associ memori
an instruct execution
a second associ memori
a first associ memori

a count/link regist
the instruct identifi tag
the control bit
the apparatu control logic set the control bit for each control buffer
specul execut of count
reset the avail bit
link/branch on count instruct
link regist
instruct in a microprocessor
each control buffer
count/link regist operand data
an instruct identifi tag
an avail bit
a set of control buffer

the data element
the latch of a stage
the input din of the current latch block
the input din of latch block the same data element
the data element befor the current stage
the current latch block
the control circuit of the stage
the avail of the data element
the announc of the avail of the data element
that data element
signal ro
signal ri
sever design of a stage for use in a fifo pipelin
other word
method for a first in first out data pipelin
an opaqu state
action of the latch
a transpar state
a signal ri from the previou stage

a counterflow
variou embodi of the invent
the second direct
the pipelin in a second direct counter
the flow of data element in the pipelin
the first direct
the basic form of the pipelin
opposit direct
multistag counterflow pipelin processor
everi data element
each stage in the pipelin commun
distinct data
copi data
circuitri at each stage
associ memori
a varieti of applic in signal process
a seri of similar stage
a second data stream of data element flow from stage
a linear fashion
a first data stream of data element flow in a first direct from stage

a counterflow pipelin processor with instruct packag
the sourc valu
the scoreboard tabl
the scoreboard
the same pipelin
the result from previou instruct
the record of regist valu
the counter flow pipelin
that result
sourc valu
scoreboard
result packag
inform flow
a record of the regist valu

a cpid
valu of coprocessor
the queue 4 word
the pipelin in the cp
the pc of the instruct
the new pc valu in the queue
the mp
the first cp
the event that an except
the entri point
the entir pc
the cp
the command inform in a single bu cycl
least 3 pc valu
cp instruct
cp
the pst
the pcid system
program counter regist
an entri point
a queue of a cp
a program statu word
a new command from the micro processor
a cpst
the cpst
pcid system

a cpu for execut
the size of the group of instruct
the memori for storag
the event of modif of an instruct in memori
tag inform for those instruct
tag inform
reduct of the valu
memori manag for scalabl compound instruct
machin with in memori compound
instruct for the purpos
group of instruct
gener of new tag valu
a hierarchi arrang memori

a cpu vendor
total number of cycl
the pipe signal
the integ
the custom actual work environ
reconfigur hardwar and/or softwar
processor within a single clock cycl
point unit datapath
point instruct queue
pipe signal
pin on an extern pin gate array
perform data
multipl instruct per clock cycl
inform on activ of key intern state
each stall free cycl
determin of custom softwar
determin of bottleneck in custom softwar on the target cpu
data cach in oper with integ
custom workload
custom softwar
central processor unit
bottleneck in an arbitrari custom workload
bottleneck
an extern hardwar monitor
addit datalin

a critic fail
varianc of cycl time
toler
third mean
the variabl frequenc oscil
the system clock cycl time
the second mean
the instruct by the first mean
the detect of the error by the second mean
second mean
recoveri code
maximum cycl time restrict
fault toler design for identif of ac defect
error in a comput system
depend defect
defect
data in system cabl
cycl time of the first mean in respons
certain ac
ani cycl time depend latch
a first mean

a critic organ
z2 in parallel
the two input primari data
the three input adder of the secondari data
the secondari data
the prerequisit operand
the prerequisit instruct
the instruct unit decod the instruct sequenc
the appar input operand from the prerequisit
the addit capabl of the secondari data
simultan pipelin
secondari data
processor for parallel execut
prerequisit operand
number of case
no instruct interlock
facil with addit capabl
facil emul the result of a two input adder of a primari data
facil adder
execut of depend instruct until operand
certain oper the simultan process of the prerequisit instruct
at a time execut
a secondari data

a critic path on the processor
the use of the superscalar featur
the end of the pipelin the destin
the dispatch unit of a superscalar processor check for regist depend among instruct
the dispatch
the correct portion of the regist
the appropri instruct in the group
regist depend check for pair instruct dispatch in a superscalar processor with partial regist
perform increas becaus more kind of instruct
older code
instruct with destin destin depend
destin regist depend
a portion of the regist

librari
tool
the graph

a cross modul boundari function call
the compil process
that function entri point
tabl pointer
tabl locat
tabl address comput in a posit
pointer logic instruct
modul access
librari sourc code into librari
entri point
each function entri point

a cross refer bit
trace array
the trace array
the occurr of an error
the master array
the complet of quiescenc
quiescenc
quiesc
master trace array
error regist
error recoveri
environ after the oper
direct hardwar error identif method
area of a comput system
an event trace identif code
an error flag
a record of the event
a cross refer event trace indentif code

a crossbar
vliw
use of a delay element
the same perform a a true multiport memori
the function unit output
port of the separ memori unit
output of a group of function unit
long program instruct
collis without an excess number of port
collis for access
an imit multiport memori circuit
all oper under control of a single seri
a smaller circuit area
a respect function unit input
a read port
a plural of separ memori unit
the branch destin address of the branch instruct
instruct until an instruct
first read
each address
delay branch instruct in delay slot
an nop instruct
address from the address
a delay slot of the instruct

protocol bit
the rout open packet
the global router network
scalabl processor
router chip within the global router network
redund address bit
parallel system
parallel comput system
method for parallel process array
an expans tap for processor
a rout open messag packet
a multipl crossbar person
a global router network

a crossbar interconnect
variou embodi
thi single chip
the usual function of buss
the interconnect chip of the present invent
programm interconnect chip for comput system function modul
programm delay
pre store control pattern
other oper
input/output port
crossbar
variou grant circuit
wire between router circuit
the section
the router circuit
the router chip into section
the router chip
the hyperbar configur
the crossbar configur
same circuitri
router chip
protocol bit circuitri
output wire avail
novel diagnost circuitry/or
novel
logic level
hyperbar
grant circuit per channel
grant circuit
enable/dis input termin
either enable/dis output termin of grant circuit in an adjac section
each input
control switche
a single output channel
a section
a same output
a router circuit
a hyperbar switch
a group of output termin of the router circuit
a group of input termin
a differ set of grant circuit
applic for the chip
an effici link between system function modul
a pipelin regist file
a custom chip

a crosspoint switch
the ppp
the function circuit
the crosspoint switch
the compon of the ppp
statist modul
pyramid processor for imag
other use process devic
more function circuit
intern rout circuitri
extern output channel
extern input channel
data between the frame store control
compens
the subsequ stage regist
the proper transfer of inform between stage
the previou stage data
the inter stage delay
compens techniqu of the invent
avoid techniqu for pipelin processor
associ
an intern frame store control
adders/subtractor

a current ata adapt
those word
thi interfac function
the physic limit of the ata cabl
the fast transfer mode
the error detect featur
the error correct featur
the error correct
the data integr
the data correct featur
signal with cabl signal transit
side of the interfac
mb/sec
local bu adapt for disk drive
interfac circuitri
full backward compat
fast ata compat drive interfac with error detect and/or error correct
earlier version of the ata
detect featur
detect capabl
current ata devic
connector a current ata system
connector
bu driver
ata backward compat
ata
an ata compat drive interfac with error correct
addit word in a data
a new ata compat transfer mode
a legaci comput system

the reg interfac
a reg interfac

second function unit
the second function unit

a current microinstruct on the microintruct
the single cycl function unit upon the condit that the single cycl function unit request access
the single cycl function unit
the scbok line
the scbo k line
the multipl cycl function unit
the instruct on the microinstruct bu i
the eu
the condit that the eu
single cycl function unit
second microinstruct
regist in the regist file
multipl cycl function unit
mean in the regist file disassert the scbok
interfac between a regist file
first microinstruct
an interfac protocol between a microprocessor regist file
an eu
a scbok line
a plural of second function unit
a plural of first function unit
a plural of clock cycl
a number of single cycl
a microintruct

a current mirror row driver
thi isol of the read current
the read row line becaus the read row line
the read row line
the read current i
the read current
the local node by a read switch transistor
the current in the row driver
the bit line
the bistabl storag latch sinc the read transistor
the bistabl storag latch in the cell
the bistabl stabil
stabil
other read port
mo gate
intern node of the bistabl storag latch control
high stabil cmo multi port regist file memori cell with column isol
gate the read
gate of the read switch transistor
gate of mo
current mirror row line driver
better control of the read current
addit read port
a memori cell
a local node within the memori cell

a current valu of the specifi size
the memori access instruct
retriev
the loopabl instruct
the execut of instruct loop with minim instruct
the detect of an access fault
rerun upon the resumpt of instruct execut
correct of the caus of the fault
an extern memori all essenti inform
a particular sequenc of a loopabl instruct
a loop mode
micro oper code
micro op code
memori size evalu
memori inform of a specifi size
a subsequ evalu of the specifi size
a memori access instruct

a current young bit
young bit reset
valid entri
the young bit state
the young bit of the broadcast entri
the same processor
the result of i specul instruct
the past young bit yi
the oldest annex entri
the destin regist address of that entri
the content of yk
the annex
restor of the previou valu of young bit in the annex
restor of the correct young bit
reconstruct of young bit in annex
n past young bit
n clock cycl
more past young bit
long latenc mispredict
execut branch
everi machin cycl
each annex entri
branch condit resolut
both embodi
all valid entri
all other entri
all k
all annex entri
age
a small constant time
a new annex entri
a first embodi

the curv from input signal
point along a path defin curv
input point
an output devic certain render data
an output devic
an input devic in respons
an imag of the curv in real time
a processor output

a curv
the non linear coeffici
origin non linear summat term
new valu
new input
method map non linear coeffici of depend control variabl
linear combin
constant time curv
actual input point
a user in real time a the user

a curv length
the number of point
the interact imag
the curv a the user
good of fit of a curv
curv length approxim
curv
control by a user
a user in constant time
a length of a curv

a custom comput system
the payment gateway system
the custom by the merchant
a plural of comput system over a public commun system
a payment gateway comput system
a merchant comput system

bu interfac unit
the gp cpu
parallel with execut of gp instruct by the gp cpu
intern memori
intern bu
gp instruct
extern memori array
execut of dsp command list code instruct by the dsp modul
dsp modul
dsp command list instruct
command list code instruct
cpu core
both instruct
access by the gp cpu for storag
access by the dsp modul for retriev of command list code instruct for execut by the dsp modul

a cycl acknowledg
the state inform under the condit that a back off condit
the resumpt request
the cycl queue
the cycl acknowledg
intern devic of a processor
intern devic
cycl queue data
cycl queue
an intern devic
a resumpt request
a queue input
a cycl under the condit that the back off condit
a cycl queue

a cycl per instruct
the perform of a data
system in order that the design
such analys
finit analysi
edg analysi
bandwidth analysi
an instruct parallel analysi
a plural of counter count sever event
a perform monitor

a cyclic oper
time sharingli make the vector processor
thi vector processor
these unit
the vector regist control
the result of oper into the vector regist
process into a plural of fundament process unit
iter process
data from vector regist
a remark increas in hardwar
a pipelin control method
a phase gener

static random access memori
simultan request for access
dual port function
dual port
control access
circuit surfac area
circuit memori
an address collis detector
a single port sram array
a single cycl of a clock
a lower cost

a d flip flop circuit
comparison circuit
a refer voltag circuit
a refer voltag

simultan execut
the instruct of the queue in accord with the number
the instruct decod in accord with the execut state of the instruct
the instruct decod in accord with an issue state of the instruct
success address
issue instruct
instruct in the instruct decod
devic in a parallel process
avail instruct in the queue
address in the queue in accord with a storag state
address in the queue
a superscalar type
a scope
a read queue address

a data access conflict
the instruct combin unit
instruct befor the result
instruct against sourc regist of subsequ instruct
execut of the subsequ instruct
an instruct combin unit for a microprocessor

a data arithmet logic unit
the data alu
the consecut instruct
power reduct in a data
more consecut instruct
ident destin for a result
back
a seri of instruct
a mac

a data array
the output of an address array
the main memori system
the i/o system of a larg data
peripher memori interfac control a a cach for a larg data
memori access request from a number of differ peripher devic
main memori at that main memori address
main memori address
data in the data array
data array in turn
an interfac control
an associ memori
actual main memori access
a number of data word
a data array address

a data chang over unit
the first storag unit
more support unit
a second storag unit
a first storag unit

thi set
the perform level of the relationship processor
the life of the system
the develop data
volumin data base
set of entiti
relationship the system
relationship at ani time
larg system
inquiri
initi system develop
extract of data object
entiti
concurr oper use of the system
comput program code
complex inquiri
commerci data repositori
a scope of design requir
a method of data

a data compress oper
the filter bank of the present invent
the filter bank
the commun
the circuit size
that embodi
pass of the 2-dimension idct
pass of a 2-dimension dct
other filter in the filter bank
filter in the filter bank
each filter in the filter bank
digit fir filter in a filter bank
circuit implement
ani implement
an imag compress
an data decompress oper
an 8-point idct
an 8-point dct

a data control flow path
verif check of each ic devic
tradit cpu function
the processor architectur of the test apparatu i
the pin of the dut
the pin check test
the orient test
the orient of the dip in the test head
the orient of the dip in the devic contact
the execut of a test
the direct of orient
the contact termin of the test head
the apparatu test head
sequenc through the test vector for the variou dut
non destruct imped measur test
ic compon test
function check
each devic under test
automat ic dip compon
an address control flow path
a pin check residu voltag measur test

a data corrector
the quotient
the polynomi divid
the numer
the further polynomi divis
the error locat polynomi determin
polynomi divis of a numer
polynomi divid
iter of polynomi divis
euclid
both equat
an error syndrom
an error locat polynomi determin apparatu
an error locat
an error inform determin
an error correct apparatu
a second coupl unit
a quotient
a polynomi divid
a first coupl unit
a denomin

comput instruct
variou machin condit
variabl program condit
the select algorithm
maximum util of the instruct
instruct select in a two program counter instruct unit
instruct an apparatu i
differ instruct stream
certain check upon the specif instruct
capabl of the instruct unit

a data depend check circuit
use in a comput
the tag onto the read address port of the regist file
the tag assign circuit
the locat of operand
the data depend check circuit
the data depend
system for out of order execut of a set
superscalar risc instruct
read address port
more tag
instruct operand
destin regist field
data depend between the instruct
an instruct execut unit with a regist file
address sourc
a tag assign circuit
a set of regist file port multiplex

a data depend cost
the total cost
the lowest total cost
the execut time of an instruct block
the current elig free instruct
the cost heurist
sum of a plural of cost heurist
point ratio cost
point queue cost
overal effect
apparatu schedul instruct of an instruct block
a store ratio cost
a resourc depend cost
a number of the cost heurist
a depend wait cost
a depend cycl cost

a data depend relationship
unit output a detect
the memori stage arithmet unit
the load instruct ld
the load data in a memori stage of the subtract instruct sub
the data depend relationship between a load instruct ld
a subtract instruct sub
a memori stage arithmet unit

resourc conflict
no resourc conflict
execut of gener purpos multipl instruct
depend among the instruct
concurr issuanc
a single clock

a data depend scheme that access data from memori
variant
the sign valu of data
the sign of a load data
the opcod depend scheme
the data depend scheme
sign
virtual address translat
the portion of the pipelin
the pipelin portion
the complet of the servic
re execut such stage
pipelin throughput
normal instruct pipelin
more interlock
interdepend
instruct latenc
multipl consecut load instruct
load data from memori
fast clock speed
differ scheme
data from memori
cycl if the load data
cycl if the data
an opcod depend scheme
all load
a delay return scheme

a data entri decod
the second address regist
tag comparison
parallel in the same clock period
lower order bit of the content
a tag entri decod
a second address regist for a data memori
a first address regist for a tag memori

a data input latch
the next stage in the pipelin via a data output latch
non overlap clock phase
a valid line
a pipelin structur process data in a seri of stage

a data input regist
util in a subsequ calcul
thi valu from the output valu
thi auxiliari valu
the variabl in the regist
the variabl in a present calcul
the subsequ calcul
the second multiplex
the pe
the input vector of data
the entir pe
pass of data through the pe
output into a data output regist
non delay algorithm
feedback regist configur for a synchron vector processor
data through a plural of parallel process element
anoth auxiliari regist
an instruct gener rom
an auxiliari regist
a variabl i
a serial video processor

a data input/output unit
valid data posit
the valid data posit
the origin order n piec of m/n bit data
the extern memori for storag
the data input/output unit
pipelin inform
pipelin control condit
pipelin condit
pipelin activ condit
n piec of m/n bit data
memori access devic
m bit data unit
data from an extern memori
data from a data
address from an address
a valid data
a number of stage select devic

a data interfac for dual execut unit
thi virtual tripl port array architectur
the same data array locat
the same cycl that the cach
the same address that a read
the other port
the end of the cycl
the array architectur
simultan cach reload
separ sequenti oper
function around the array
featur of the cach
execut unit access
back to back read access
array design
a half cycl

a data measur devic
use method
the user interfac
the artifact with the time
qualit inform
posit inform
physic condit
other measur devic
manag personnel
artifact in a time
artifact from the user
archiv record of data
an artifact
an accur time
a user interfac
a use project manag tool for the user
a time scale
a gp receiv

a data memori in respons
the condit test
success data
execut of data
each memori access
condit test
condit control
complet execut of a current instruct

a data memori while instruct
type inform
operand data for use by thi instruct
more rapid execut of instruct
extern storag unit

a data ouput latch
these match a data output
the present address
the memori cell array
the last address
the appar access time
semiconductor memori devic with pipelin access
last address
an on chip self increment counter
address input termin

a data out latch
the lpbi
state machin with a configur regist
high perform peripher interfac with read ahead capabl

the output unit
an output unit
an input unit

a data packet from a transmiss path
transmiss of a data packet on the transmiss path
the transmiss control unit
the output of the latch circuit for output of the oper
the output of the imag
the output of the alu
the instruct code from the pipelin regist between data from the pipelin regist
the instruct code from the pipelin regist
data from the pipelin regist
a transmiss control unit
a seri of complex oper
a result of a seri of complex oper
a gener number

a data packet output from the plural
the plural of output
the content of the input data packet
output the input data packet
an output control portion
an input data packet
alloc method
a plural of output

a data packet storag locat
the oper of the host processor
the minimum back to back separ
the media access control unit of the commun control
the commun control buffer
statu queue
statu control interfac unit of the commun control
respect statu bit queue
respect queue
recept of data packet
network data
due cours
data packet storag locat for these command
data packet storag locat
data commun oper within station of a local area network
data commun control within the commun control of station within a local area network
consecut transmiss
commun event of the same type
command queue
a result of the present invent

a data pointer
thi comput processor complex i
these multimedia instruct
the multimedia processor over a second bidirect port
the multimedia instruct
the hardwar processor over bidirect port
the hardwar processor
the data pointer
the comput processor complex
the bidirect port
the address in memori
regist for a program counter
multimedia function
load separ instruct stream from main memori
commun mechan
a visibl regist
a stream of non multimedia instruct in addit
a stream of multimedia instruct
a second bidirect port on the visibl regist
a multimedia coprocessor
a main memori devic
a hardwar processor
a first bidirect port on the visibl regist

a data predict address
the stride valu from a locat within the data predict structur
the stride valu
the data predict structur store
the data predict address
stride valu in a predict array
stride base data
predict structur
data byte into a reserv station
an instruct each time the instruct
a data predict structur

a data processor control unit
the prefetch instruct address flow
servic instruct
prefetch instruct address flow
normal instruct word befor complet
no instruct execut cycl of the data processor
instruct prefetch redirect
instruct for execut by a data processor
instruct cycl boundari
data processor control unit
address gener befor complet of execut of normal program instruct
actual instruct
a prefetch counter

a data processor for execut
the tag part from data on a data
the tag part
the control on the basi of the output of the regist
tagless data
tagless
tag multi way jump
part under the control of the micro program control
part for address comput
an extend
accord with the evalu result of the tag part
a tag part
a tag multi way jump encod
a tag multi way jump address
a signal from the micro program control
a plural of tag part
a micro program control

a data processor in accord with the present invent
the subroutin return instruct in an instruct
the return address from the subroutin
the pre branch process
the pc stack
pre branch process with respect
pc
onli return address of the subroutin return instruct
a subroutin return instruct
a subroutin call instruct in an execut stage of a pipelin
a stack memori
a return address in the initi stage of pipelin

the microsequenc
a microsequenc

a data processor microsequenc
the upc
the next microinstruct address
the next microaddress
the nanorom
the microrom decod the next microaddress
the microrom decod the initi microinstruct address
the macroinstruct
the initi microinstruct address
the entri pla access macroinstruct from an instruct pipelin
subsequ microaddress in the microroutin
strobe circuitri
n output bit
decod the macroinstruct
an initi microinstruct address for the microroutin
an initi microinstruct address
an entri point pla
an entri pla
activ either the microrom
a non multiplex intern address bu i
a next microaddress output of a microrom
a nanorom
a microrom
a microprogram counter latch
a macroinstruct address

a data processor of the present invent
the oper inform for the operand of the instruct after complet of address calcul
part of a multipl oper instruct
mode into a pipelin
load at each stage
each design
a whole apparatu increas

a data processor system
the other pipe line i
the memori control unit via interfac line
the main memori unit
main memori unit
each multiprocessor system
each memori control unit of each multiprocessor system
data throughput in a multiprocessor system
channel control unit
anoth memori control unit
anoth main memori unit
a plural of multiprocessor system

a data qualif
the vehicl diagnost instrument control
the test diagnost system
the rate of data
the instrument peripher interfac
the instrument control
the arbitr control
independ instrument channel
high perform automot diagnost instrument architectur
high data rate
an instrument peripher interfac
an instrument control
an automot test diagnost system
an arbitr control
a vehicl diagnost instrument control
a first bu
a devic interfac
a data storag

a data receiv
the retransmiss request signal i
the retransmiss request
the data transmitt
the data receiv
retransmiss data
end in a pipelin fashion
data transfer devic
data in the fifo memori
data in a data
a retransmiss request
a fifo memori in a pipelin fashion
a data transmitt

a data record
the second sensor section
the pipelin in a counterclockwis direct
the first sensor section
the drive mechan
second sensor section
second sensor
rotat direct
multi direct magnet flux pipe inspect
helic sensor signal pathway
first sensor section
field interrupt data
a second field gener
a plot of anomali in the pipelin
a pipelin inspect pig
a grid
a first field gener
a drive mechan

a data respons from memori
the pipelin for most instruct sequenc becaus bypass logic make avail data operand from memori at the second alu stage with an appar load latenc
the first alu stage
the first alu if the result
potenti loss of overal perform
other arithmet oper
memori at the end of the cycl
a subsequ load instruct
a six stage pipelin processor

a data stack
the remap array
state of oper while specul instruct
remap array
point stack
outcom of branch condit
multipl instruct in a single cycl
exchang instruct
a stack exchang capabl
a remap array
a lookahead stack pointer

a data stagnat detect circuit
use of handshak control signal
the feedback stage
the data stagnat detect circuit
the control stage
static data
no data stagnat
enabl of the feedback circuit
a plural of parallel static type data
a plural of control stage
a particular control stage
a field effect transistor
a feedback circuit
a datapath
a data stagnat in the datapath

a data storag address
the top of the instruct address stack
the stack regist in prepar for the next return instruct
the same data storag devic
the perform of the pipelin
the next instruct store address
the next avail instruct store address from the instruct address stack
the instruct store address
the instruct storag
the instruct from an instruct storag
the instruct address stack in the data storag
the flow in the pipelin
the data storag
stage of the pipelin until sever instruct execut phase
stage of the pipelin
instruct phase in the pipelin
instruct address stack in the data memori of an instruct pipelin processor
datum in accord
an intermedi stage in the multipl phase instruct pipelin
an instruct pipelin for a data processor
access stage
a stack regist
a stack pointer in a stage of the pipelin between the instruct
a sequenc of phase
a return oper
a return address stack in the data storag
a datum operand

storag element
point execut trap

a data storag structur
the storag element
the precis state
the issue unit issue instruct in program control order for execut
the first execut except
program control order execut data processor
program control order by the execut
point trap type field of the storag element
point trap type field
point statu regist
point execut except
point except unit a precis state unit
point except unit
non float point instruct
float point except
field of the storag element
execut except
engag in execut trap
each storag element
an issue unit
an execut except
a second execut except

a data stream
the group of page
sheet
print command
pre print command
portion of data stream upon error detect
more page data block
more oper
group of page
accord with the command in the data stream
a print processor
a group of print data page in the data stream

a data stream process pipelin
output latch arrang
error correct code pipelin
embodi of the present invent the input
data from a storag devic
an output latch arrang
an input latch arrang

a data transmiss between tray
unit into a plural of group
the number of unit
the data transmiss time
the data transmiss in a system
the connect state of the data transmiss path between tray
system process data
parallel process method
neurocomput oper
excess unit for anoth oper
an independ oper
a tray connect
a plural of tray
a neurocomput oper
a neglig data transmiss time
a matrix oper

the temporari regist
a temporari regist

a data type transfer instruct
writeback for data
type of instruct
type instruct until the writeback stage of the next data
type instruct return at the end of the writeback stage
the writeback stage of the next data
the write of the data
the result of the data
the result of instruct
the proper execut block
the prior art processor
the layout complex
the data from the temporari regist
the conflict of resourc
the amount of silicon area
regist file
extra instruct stage
an integ execut unit regist file
all integ instruct
a regist file with 32 separ regist
a four stage instruct pipelin

a data valid signal
the data valid signal
data valid signal
a read data
a read address
a limit

a datastream
the pagemap by parallel bin processor
the datastream
store state independ block
request prepar of often use resourc
pelmap
parallel raster
parallel processor in all stage
parallel block processor 22 convert
pagemap bitstream
intermedi form data object
geograph region of the pagemap by parallel sort processor
gener purpos microprocessor for all stage
end of block marker
correct order of the object within the final pagemap
a scan processor
a raster

a date
time field
the token with a transact request
the token for that row
the then current time
the same termin
the date time valu
the conclus of the transact
the associ of the transact with a uniqu termin identif
anoth non concurr transact
a token with a null date time valu
a token tabl
a termin identif
a queri oper
a plural of transact from a single point of initi
a plural of transact from a single initi point
a particular token
a null valu in the date time field

a datum
the second destin regist
the out of order load instruct
the newli read datum with the datum
the newli read datum
the first destin regist
the datum read by an out of order load oper
system store sequenc of instruct in a memori for execut by a processor unit
such out of order load instruct
origin posit in a sequenc of instruct
dynam reorder of instruct
data comparison
coher among memori
an out of order load instruct
an interfer test
an earlier posit
a second destin regist
a recoveri sequenc
a locat in memori
a first destin regist
a datum from the same locat in memori

a ddcp oper
these request
the throughput of proof imag for the ddcp system
the throughput of proof imag
the rip
the ddcp system
that proof imag
system in a manner
success proof imag
request from remot station for proof
re priorit proof request
proof request in a direct digit color
proof request
oper interact with the system
onli paramet valu
hard file
engin in the ddcp system without substanti oper intervent
each proof
chang the order
chang individu paramet valu in each proof request
a substanti number of these request
a proof request queue within a raster imag processor
a first in first out basi

a deadlock condit
the local store access signal i a read access
the local store access signal i
the local buffer in respons
the local buffer
the high imped state
the extern access signal
the extern access
the deadlock resolut logic
the deadlock condit
the cach control for perform
the address store
the address storag devic
the address for the address store
system resourc for access
high imped state after the read access
extern access signal
deadlock resolut with cach
deadlock resolut
deadlock between a local processor
control of the local bu
an address storag devic
address in respons a local store access
a sequenc of control signal in respons
a local store in a multiprocessor data
a local store access
a deadlock detector

the vacant entri identif
the vacanc within the reserv station for storag of instruct inform
dynam approach
a number of vacant entri of a buffer resourc

a dealloc vector of a reserv station
vacanc
the vacanc search
the reserv station for subsequ execut
the dealloc vector into separ portion
schedul a group of instruct from the instruct decod
prioriti refer point within the dealloc vector
point for vacanc locat
method for entri alloc for a resourc buffer
consecut vacanc
consecut bit
bit of the dealloc vector

a debug
the state of the normal mode of oper
the other mode of oper
the debug mode of oper
supervisor address space
normal mode of oper
instruct from the normal instruct set of the processor
execut unit each unit
emul mode of oper
emul command at normal processor
an exception/interrupt
an altern oper mode of the processor
access user address space
a uniqu debug address space

the integ instruct
an integ unit

a debug mode of oper
the processor system
the debug mode of oper with precis except
receipt of an instruct
oper in the normal mode
debug mode for a superscalar risc processor
a multi stage integ pipelin

a debug modul
the user program
the monitor program
the debug tool
the debug modul
make
except request
debug system
an interfac with a debug tool
a user target system
a user program
a monitor program

a decim
variabl length code
the video signal interfac
the instruct set of the central process unit
scene analysi
redund in video signal
other signal process function
numer featur in support for such featur a alpha filter
multipl coprocessor implement dct
motion vector at a time
motion pictur
memori manag
idct
adapt threshold filter
absolut differ
a video signal encod under the mpeg
a matcher
a format

a decim calcul unit
way of a cach memori
processor with larg instruct set
point calcul unit
own command block
ead
the last microinstruct
the instruct in progress
the execut of the microprogram of the instruct in standbi
the execut of the microprogram of the first instruct
the execut of brief instruct
processor with a plural
instruct in pipelin manner
execut indic
each command block
certain unit an anticip indic
bdp
the instruct in progress in each unit
the execut of the microprogram
a third unit
a second unit
anoth unit
an end of microprogram indic

a decis circuit
the statu chang
the state of the output pin chang
the presenc of the output pin that the statu chang
the output side
the logic element of the output pin
the kind of logic element
the input pin
multipl loop
mo type logic element
logic simul system
logic simul of a larg scale logic circuit
each inform read
an output side
an input side
an exchang
a logic element

a decod structur
the updat processor
the reliabl of each bit of the result
the pariti processor
the pariti equat for a block of code
the modif
tanner
soft decis inorm per clock cycl
semi systol architectur
quasi cyclic error correct block code
previou iter
more pariti processor
digit commun
convolut code
algorithm b
a modif of tanner

a delay circuit
thi problem
thi obviat
instruct befor a condit branch instruct
effici in a pipelin
an instruct memori behind a system clock
accord with a state of calcul

a delay from carri input
the adder group
some bit
intermedi group
each adder group
carri scheme
a plural of adder group
a most signific group
a least signific adder group
a high speed adder
a delay from operand input

a delay in the preparatori process
thi intermedi data
the prepar
preparatori processing
oper of the command inform
numer control method with a parallel process function
interrupt of the numer control
form data
execut of each preparatori process
each start
command inform
block of the nc program
apper
an intermedi data
accord with variou kind of nc program
a numer control method

a delay of the data
the relev modul
the process of data
the data whereto the signal
the advantag that the number of connect between the modul
synchron with the data
process the data
pipelin system with parallel data identif
delay of data identif signal
correct data
all modul
a pipelin system in accord with the invent
a modul by a delay

a delay resourc
video data from the upstream end
the video data
the oper of the processor
the host comput
the downstream end of the plural of channel
the downstream end
the crossbar switch
real time line scan processor
line scan sensor
line scan camera
an upstream end
a video data
a plural of parallel channel
a high resolut imag of an object
a downstream end

a delay valu
time inform
the second type of instruct
the delay time
overal process of the softwar program by the system
non branch instruct in the basic block
non branch instruct
instruct of a second type
instruct of a first type
instruct in a first order
instruct in a differ order
instruct in a basic block
faster branch execut
a variabl number of instruct cycl
a time of execut of the branch instruct
a time of execut
a processor element

a depend between instruct
true depend in an out of order processor
true depend
the valid of the entri
the valid inform
the sourc regist of the current instruct
the process inform
the age inform
more compar
inform about the age of the entri
fals depend
an instruct identifi
a depend tabl track instruct depend between a current instruct

a depend checker
the preced matrix
the m oldest instruct
the m
the elig queue entri signal
the depend checker
the avail regist
the age of the n instruct
store n instruct in an instruct queue memori
m instruct per clock cycl
instruct without data depend
execut unit for execut
avail signal
an oldest instruct selector
an instruct selector
a preced matrix

the data result
the temporari data regist until all prior instruct
the instruct for out of order execut by the function unit
the instruct execut control unit
superscalar-bas comput system with out of order instruct execut
sequenti program order
resourc util
perform throughput
length instruct
data result
a set of temporari data regist

instruct for execut
concurr result distribut

a depend checker unit
the comput system architectur
retir control unit
program instruct set
optim the schedul of data path in accord with the type of comput function
a temporari buffer
a regist file array

a depend on an oper execut mechan
the order of the oper execut
the order of oper execut
the oper field of the instruct code
the oper field
the number of the oper
the number of oper field of an instruct code
the number of oper field
the necess of a null oper
the format field
parallel by a number of decod
more type of oper
effici of instruct
all order of execut of oper
a vliw type data processor
a specif function
a format field

the scientif processor
the high perform storag unit
a vector processor modul

a depth buffer techniqu
visibl object
those object
the use of processor
the shadow affect
the pariti of the number of intersect between shadow polygon
shadow correct valu
requir
vector storag circuitri
vector operand
vector multipl
vector move
vector file storag circuitri
vector file
vector control circuitri
variou combin under program control
the vector processor modul
the scalar processor modul
the refer cycl of the high perform storag unit
scientif processor for use in a data
scalar manipul
result operand pair at a rate
oper control of the host processor
instruct function of vector addit
instruct flow control circuitri
compar rate
a scalar processor modul
a scalar processor arithmet logic unit
a high perform storag unit
a gener purpos host processor
rapid evalu of a larg number of object
graphic system shadow gener
determin of the effect of a shadow
calcul of visibl shadow
a shadow gener method
a shadow
a line of sight

a depth regist
surfac elimin in a time divis fashion
plane segment inform
pixel processor
pixel on a horizont scan line
lsi implement
intens data
each pixel processor process
direct in the array
an intens regist
an intens data output
an intens data
a high imag output rate
a hardwar of the pixel processor

a design regist name rj
the plural of context
the context
pipelin vacanc
multi context processor
cidi a a context id
anoth context
an instruct of a certain context
an id
a vacanc of the pipelin
a plural of context
a peculiar context id

a design verif system
the test system
the respons of the devic
the respons of a devic under test
the input stimuli
the correl
test coverag for the devic under test
qualiti of function verif
iter test of a devic under test
correl engin
an automat correl
a set of test stimuli for applic
a pseudo random exercis
a new set of stimuli
a devic under test

a destin address gener
the sourc address gener
the pipelin control for priorit of data
the intern memori interfac
the extern sequenc
the extern memori interfac
the destin address gener
request priorit circuitri
oper in mani case
instruct cach servic request
extern memori interfac
destin memori oper
destin data word size
data word boundari
control signal for the extern memori via the extern memori interfac
buffer circuitri
architectur of transfer processor
an extern sequenc
a sourc address gener
a further cach buffer

a destin devic
the other compon
the logic i
the graphic subsystem
the amount of inform
high speed
both imag
a vector address gener for effici gener of memori address for regular address sequenc
a set of high speed data buse
a seri of vector processor
a seri of polygon processor
a parallel vector

a destin float point regist
the float point unit of the processor suppli
the appropri operand input
second instruct sourc operand
regist for parallel process in a microprocessor
operand input
imaginari compon
dual oper instruct
dual oper algorithm
appropri interconnect
anoth regist
an intermedi result of the multipli unit
an adder unit
a float point execut unit
a float point bu control

a destin for an output
the immedi data format
the destin field of the previou instruct
the content of the input pipelin latch
the alu output of the previou instruct a a second operand
prior instruct
microprocessor system with flexibl instruct
an immedi instruct
an immedi data format
a pipelin comput architectur with an input pipelin latch
a field for intermedi data

a destin identif
virtual identif of a multipl context
virtual identif
thi multipl context
the number of multipl context
the multipl context
the function of the multipl context
the data of a current configur
the configur control
other multipl context
multipl configur memori context
local control
element of the array
element in a network of multipl context
each multipl context
destin identif
data of a current configur
configur control signal i
array of multipl context
an address mask
address mask
a number of configur memori context
a multipl context

a destin operand
unit preprocess
the stack pointer
push
the sum of all increment
the stack valid array
the stack top address in memori
the stack top address
the stack pointer from the regist file
the stack memori
the overal displac
the new stack pointer
the increment amount in the stack valid bit array
the increment
stack push/pop
sever stack instruct
other stack instruct in the pipelin
increment valu
decrement for stack instruct in the pipelin
decrement amount for stack instruct in each pipelin stage
an overal displac
addit shadow regist for stack pointer of instruct in the pipelin
a stack valid bit array
a doubl width data
the same manner a conflict for express specifi
the same data path
the express specifi
specifi in the same fashion a express operand specifi
specifi in addit
some common instruct
short liter specifi
read specifi
queue between the instruct unit
perform gain
more complex instruct
bsr
autoincr
autodecr of the stack pointer
access type

a destin operand field
the sourc of a pop instruct in a pipelin comput
the pop instruct
the oper code field of the pop instruct
the execut phase in respons
the destin for the pop instruct
inform from the stackpoint
inform from the destin operand field
execut by an execut stage of the pipelin
a pop instruct

a destin queue
the destin queue
a sourc queue

a destin specifi from the destin queue
write operand queue
the write pend bit
the issue pointer
the entri of an instruct
the destin specifi
specifi from multipl instruct
sourc specifi
read after write depend scoreboard
read after write conflict
obtain sourc specifi of an instruct from the sourc queue
execut of a plural of instruct
execut of a current instruct
each entri of the queue
destin specifi in the destin queue
construct
conflict between the sourc specifi of the current instruct
an oper upon the sourc specifi
an issue pointer
an instruct decod decod
a read pointer

a detach keyboard
the screen with the pen
the report
the keyboard
succinct input from a user
subsequ inform
report in respons
report
electron document system
appropri item
anoth system
ancillari inform
a report
a portabl comput system
a pen
a method of the present invent

a determin that the indic of the instruct
the second prioriti group
the particular posit within the regist
system in a superscalar data
system for the effici handl of except
indic of multipl instruct while the multipl instruct
a second prioriti group
a particular posit within a regist within the data
a first prioriti group

a devic plug of the emul head
vlsi devic
the vlsi devic
the target machin
the in channel emul capabl
the emul control monitor instruct
the emul control
mo microprocessor
in circuit emul for gener vlsi technologi with capabl
emul for non fix instruct
an emul for non fix instruct
a vlsi devic in a target machin
a varieti of vlsi devic
a socket in the emul head
a microprogramm emul control
a devic specif emul head

charg
the instruct setup unit
multipl instruct setup unit
instruct schedul unit
instruct from plural instruct stream into plural instruct execut unit
instruct a the first half of the procedur in instruct pipelin

a devic that substract electr charg
the array of ccd
the algorithm comput
multipl calcul
laplacian convolut
group of ccd
ccd
an array of charg
all comput in real time
algorithm comput on a set of data
algorithm comput
a focal plane imag processor

a diagnost processor
unnecessari diagnost action
the mayday
instruct attempt
error in a pipelin data processor
a seri of pipelin stage
a mayday signal i

a diagnost test pattern
transposer/compressor assembli
thi respons
these entiti
the diagnost apparatu of thi invent
normal process condit
imag processor entiti
diagnost system
commun with resequenc

a differ algorithm for unit delay simul
unit delay simul in a high perform
the multi unit delay time queue manag
the machin
the logic simul function
simul mode
multipl simul time unit
dual delay mode
a single stage of a six stage pipelin

a differ amount of time
the same amount of time a the other processor
the individu processor rate
synchron multiprocessor
rate of the individu processor
processor at rate
output data buffer
multiprocessor architectur
input data buffer
individu processor
asynchron architectur
an output data stream at time
an input stream of data
an input distribut function
a differ rate

a differ between a z valu czf at the front
ze in a view volum in a viewpoint coordin system
z in a screen coordin system
ye
the z valu czf
the z valu czb at the rear clip plane
the view volum
the rear clip plane
the differ between the z valu czf at the front
plane posit
perspect transform of three dimension object
data xe
data x
data bit of the z
czf/ze
a z valu czb at the rear clip plane
a z buffer method in accord with the z
a rear clip plane
a hidden surfac remov oper
a front

a differ between the valu of read
wave number
the system in addit
the logic delay line
the delay pipelin
the delay line
second multiplex
repetit rate for read cycl
part of a configur of the processor
gener of control signal from the read cycl rate
discret delay
data valid window
address cycl
a wave pipelin read control
a wave number
a repetit rate for read data
a plural of clock delay element
a logic delay line

a differ clock number
time for the processor
the specif inform
the oper of the pipelin control mechan
system for automat gener instruct
pipelin oper of a processor
input about a pipelin process of a plural of instruct
high reliabl for variou processor
each pipelin stage of the instruct
differ pipelin stage configur
a plural of similar pipelin stage
a differ configur

a differ codebook vq
the special case of a binari tree search vq
the faulti pe of the array
the end of the array
systol binari tree search architectur for vector quantiz
systol array architectur for vector quantiz
pipelin synthet apertur radar data compress
ident process element
codebook memori assign
a tree search vq
a system for data compress
a raw codebook vq
a pe
a fault toler system

multipl arbit element
more user
asynchron arbit
an arbit circuit

a differ combin of request signal
user exclus access
the plural of mutex element
the output of the arbit circuit
the other mutex element in the arbit circuit
the next grant signal i
the new state of the grant signal
the mutex element
the grant
the current state of the grant signal
mutex element
grant signal
a plural of mutual exclus
a new mutex element

a differ embodi
the sdram access
the sdram
the bandwidth maxim embodi
the amount of time data from a particular sourc
synchron dynam random access memori
sdram
next request for access
memori pipelin
current request
characterist of the latenc minim embodi
a router
a hybrid configur

a differ format for the control word
these complex instruct
sever pipelin
risc equival by the instruct decod
regist operand
pipelin valid bit encod the order that instruct
more instruct set
more control word
interlock logic
instruct in a single clock cycl
instruct from sever instruct set
dual architectur super scalar pipelin
depend between instruct from ani instruct
control word for the pipelin
cisc instruct decod
branch oper
all instruct set
a simple branch
a group of instruct at the same stage in the pipelin
a dual instruct set processor process instruct

a differ imag product in the median filter asic
tomographi apparatu
tomographi
the median filter asic
the median filter
the coordin of each pixel with refer
the angle
the access address
special hardwar in the form of a processor
point address
each pixel a determin of increment
asic
a rotat center in the processor
a result imag
a median valu format
a median filter asic

a differ instruct
the total number of clock
other operand
new operand address
mathemat oper in a processor core
an intern pointer
a sequenc of oper
a first subsequ cycl

a differ oper mode
twiddle factor
the sequenc of the dsd oper in the pipelin
the principl of oper
the fault toler oper of the pipelin in case of a partial failur
the dsd sequenc
the dsd modul
sever stage
radix
pipelin processor for mix size fft
interchang ani compon
fft of radix
element for the smaller size
diagram
ani mixtur of fft size

a differ processor
unit identifi for parallel process by a readi process unit
the serial stream
the sequenti of the output data stream
the same order a the origin
the parallel process unit
the origin order
the id of the processor
the command distributor of the invent hand out command
single command
recombin
each portion of the result
each parallel process unit request data
data into a serial data stream
consider process
command/data packet
bu arbitr hardwar
a serial stream of command
a plural of request
a parallel array

a differ regist
the use of regist for the temporari storag of the sequenc result
the store of sequenc in regist
the sequenc oper
the result of a previou oper sequenc comput
the result for each sequenc of oper
the initi oper
the comput of the oper sequenc result
the comput of the current sequenc oper
the comput of a current oper result
such result
set of regist while the final result from the sequenc oper
paramet in a progress fashion
other regist
concurr input/output oper
an interlock capabl
a seri of oper sequenc result

such microprocessor thi invent
clock cycl and/or

the modulo
on chip cach
off chip cach
multi level memori devic

the code optim pass
the address within memori load
target program instruct

a differ target comput platform
the separ between a load command
the load latenc valu
the load latenc
the execut of modulo schedul loop in the target program code
the determin of the optim load latenc an automat featur
return of the data
most modem microprocessor
invent
vector for use in modulo
the process of modulo schedul target program loop
the determin of the entir vector
minim effort
effici determin of an rmii vector for modulo
differ valu of instruct load latenc
a set of rmii valu
a single rmii valu
a rmii vector
a recurr minimum iter
modulo
load latenc valu if the target program
instruct for a target program
automat select of the load latenc
an rmii vector
an optim load latenc valu
a load latenc valu

a differenti approach
the roller
the optim level of compact
the front of a roller
the chang in varianc over success pass
signal from the asphalt
sensor
real time asphalt pavement qualiti sensor
densiti of the asphalt pavement
asphalt densiti in real time
an indic of the optim compact
a real time differenti asphalt pavement qualiti sensor of the present invent

the termin inform
those oper
the state of the machin
the decod logic
report termin inform
oper in order
n oper
issue oper
a pipelin control system

multipl oper
the unit in a manner
the resourc of the processor
the other unit
termin inform
simpler risc like oper
semi autonom risc pipelin
segment reloc
risc like semi autonom function unit in a processor
out of order manner
out of order execut of complex instruct
instruct of the target architectur
execut of risc like instruct within the multipl superscalar execut unit of a processor
decod logic
address of the instruct
a virtual architectur

a digit array signal processor
vector signal processor
the digit signal array processor
the digit array signal processor
the decim in time algorithm
the decim in frequenc implement
subtract oper
stage pipelin
nanosecond machin cycl
nanosecond
complex operand
complex number
a seri of processor
a seri of oper on an array of operand
a separ oper on an operand array
a second implement
a fourth stage for distribut of the output operand valu
a first stage for distribut of complex input operand valu

a digit audio data
time slice of the tdm
time divis
the patch bay bu structur
the destin address of a group
the bu connect structur
system for digit audio data distribut
sourc devic
recipi devic
own uniqu address
multipl recipi devic
more group address
each destin devic
digit audio signal process
digit audio devic
digit audio data
a tdm patch bay bu structur
a single time slot of the tdm
a plural of digit audio process devic

a digit circuit
the transit detector
the logic transit at the digit circuit input
the digit circuit output
spuriou transit
logic node
a transit detector
a suitabl time
a stabl logic level
a spuriou logic transit
a self time circuit
a self time approach
a logic transit at an input
a digit electron devic

a digit comput
the oper sequenc code in each instruct word
the instruct word until such oper
the hierarch preced of an oper
memori a a program counter
dictat that the next follow oper in a sequenc
apparatu for apply sourc languag statement
an operand address code
an oper sequenc code
an oper code

a digit comput aid graphic system
workpoint
two dimension coordin axe a planar represent of a three dimension pipelin
thi system featur automat select of valv
the best view
subservi point
rel three dimension coordin
materi control system
input format a a seri of workpoint
gener of command signal
fitting for use within the pipelin in accord with servic requir
descript
comput aid graphic system
automat provis of isometr coordin
automat monitor of all materi pipe item
automat gener
automat creation of purchas order
automat creaction of list of materi
automat calcul of all three dimension coordin of workpoint

a digit data processor for matrix vector multipl
respect array row
processor of the invent
output from the array
multipl by larger matric
matrix vector product bit
input vector coeffici bit
input bit
each cell mutipli an input bit of a respect vector coeffici by a respect matrix coeffici
digit data processor for matrix vector multipl
cumul sum
column neighbour
cell per clock cycl
bit serial multipli
array column
a two channel devic
a systol array of bit level

a digit imag data
the myelin sheath thick
the myelin sheath area
the fiber perimet
the fiber eccentr
the fiber area
the digit imag data
particular characterist of the nerv fiber
characterist of nerv fiber
axon area
an imag of a cross section of a nerv fiber

a digit instruct processor control system for an instruct processor
time the main microcod control
separ hardwar
microcod control signal
instruct processor control system
execut of multipl class of machin instruct
decim instruct execut
cycl instruct
control signal for execut of all pipelin stage of standard instruct
control of the separ sequenc control
binari instruct
all subsequ stage of execut
a separ sequenc microcod control for execut of certain instruct
a multipl stage instruct execut pipelin
a main microcod control
a hardwar control

a digit of a frequenc
wave
the sign of the sample
the rom with the sample
the residu data
the output of the independ adder
the output of the dual port memori on the basi
the number of independ adder
the magnitud of a sample
the individu digit
the independ memori
the frequenc synthes
the first sample
the dual port rom
sample of one quarter
residu word
residu output word
residu number system
residu inform
residu digit
quantiti
output waveform
moduli
direct digit frequenc synthes
anoth embodi of the invent
a sample
a residu to analog convert
a residu
a plural of individu adder
a plural of independ memori
a phase accumul
a dual port rom
a direct digit frequenc synthes

a digit of a number
the second light beam
the residu of the number modulo
the optic comput devic
the input devic
the first light beam into second light beam
the first light beam
the convert
residu arithmet oper
prime moduli
optic comput
one of a first plural of light
group of second light beam from the convert
group of second light beam
group of residu modulo
first light beam
each number
convers of number
an optic comput system
an optic comput devic
a second plural of light

a digit pipelin
vocod speech synthesi
vocod pipelin processor
vocod paramet
the pipelin capabl
the function of vocod spectrum analysi modem modul
the function of vocod pitch extract
temporari storag of data while comput
speech synthesi
sinusoid
signal for control of the remaind of the processor
modem demodul
data modem function
combin modem
both vocod
an impuls respons synthes
a plural of read onli memori for perman storag of function

the adc
an adc system

a digit represent of the analog input
the sigma delta modul
the analog output a an input
second digit output
high speed sigma delta adc
an analog output
an analog input
a sigma delta modul
a second digit output
a first digit output

a digit serial data format
to digit serial convert for system
throughput rate
throughput effici
subsequ process of the digit data word
digit bit width i
data in digit serial format
convers apparatu i
attend convers circuitri

a digit serial stream of data
weight in seri with the input of each columnar delay element in a row
the row output of prior row
the output of the last delay element off the last row
the output of the last delay element of each row
the output of the adder
the arrang of adder
supress imag characterist
success row of delay element of the array in horizont line length
pixel valu of a 2-d imag
pixel delay element in each row
output of the convolv
output from prior delay element
dimension hybrid digit convolv
delay element in each row
cumul adder delay
a rectangular array of delay element of pixel durat
a hybrid 2-d digit convolv in a video imag processor

a digit signal oscil
the signal processor pipelin
the power up reset circuit
the power consumpt
the digit signal oscil
reset circuit
number of clock puls
a suffici number
a power up signal
a power up reset circuit

a digit signal process architectur
these locat in the random access memori
the processor retriev a valu
the processor commun with an extern unit via a random access memori
the operand in the second stage of the buffer
the last readi operand
the first stage of a doubl buffer
the comput unit
refil that locat
output fifo
fifo
videophon servic within narrow band digit network
video codec
the vme
the local memori modul
sourc codec
numer process element
messag data for synchron
local memori modul
imag bu interfac modul
first input first
commun between the processor element
a videophon system
each sample of the input sample stream
each fifo
digit signal processor architectur
copi the data
an operand mask regist
an invis move function
a respect locat in the random access memori
a plural of fifo
a novel regist

a digit signal process circuit
throughput of accumul
the success product output of the multipl circuit
the product output of a multipl circuit
the occurr of overflow condit
the occurr of an overflow condit
the event of an overflow condit
the barrel shifter
success arithmet oper
number of least signific bit
number befor an output signal i
correct circuit
an overflow detect

a digit signal processor without data move
use in other activ
the plural of input line
the digit signal processor without further process
the digit signal processor program memori
the analog input multiplex output line
the analog input multiplex
the analog data acquisit system
support from a processor
store analog data
instruct memori locat
each analog input
analog data acquisit system
an input line
an analog input multiplex
an analog data acquisit system
an acquisit sequenc

a digit sourc
the intern memori array
the gener purpos cpu
the execut of the dsp algorithm
platform
own gener purpos task
mani applic the data
intern memori array
gener purpos task
digit signal processor/gener purpos cpu
an analog transmiss channel
an analog front end
a sequenc of dsp oper

a digit valu
the squar wave output signal i
the output of the compar a the input data
the low pass filter
the duti cycl of the squar wave output
the digit valu
success approxim analog
pwm
input the output analog
digit convers
circuit structur for use
an output of a compar
an output analog
an input port
an input data
a valu of an analog signal
a success approxim analog to dialog convers oper
a squar wave output
a pwm element
a puls with modul
a duti cycl

a dilat
the serial signal stream
eros transform in digit imag
eros
digit circuitri

a dilut
the stock solut
the dilut
tank
solut
variou implement of a memori centric comput system for dsp
single port memori
respect execut unit
reconfigur memori system
reconfigur memori architectur for digit signal process
other comput intens applic
multipl reconfigur memori segment
more execut unit
memori space between the processor
dma channel
continu execut
configur with multipl address sourc
alloc of variou amount of memori
a dsp execut unit
second pump
pump
photosensit materi processor
an empti process tank
a stock solut
a second pump
a ratio of period of discharg of the liquid
a photosensit materi processor
a photosensit materi
a liquid
a first pump

a direct antenna
the main signal in an adapt feedback loop
the auxiliari signal i
the auxiliari signal
multipl arriv time
multipath recept
more auxiliari omnidirect antenna in an acousto optic devic
good cancel
equal with the interfer
an optic signal processor
an interfer
an adapt signal processor
amplitud inform of the origin carrier throughout the optic process
adapt signal processor for interfer cancel
a spatial correl process
a function of signal delay
a first time correl

a direct cost valu
the total valu
the optimum result of each comparison in the pipelin
simple circuitri
path optim
optim problem
an optimum valu
an optimum path valu
an adjac sum valu
a processor control circuit
a pipelin parallel structur
a direct sum valu

a discret cosin processor for video signal
multipl point
each term of a discret cosin
discret cosin processor
all mathemat step
a power of 2 term

a discret fourier transform
transform valu
the signal valu of the input
the signal valu of the first intermedi array
the output array of signal valu
the intermedi section
the frequenc transform of the input array
signal valu through the input section
signal flow pattern
section of the pipelin processor
second plural
output array
multipoint pipelin processor
least n signal valu
interel
comput in a pipelin fashion
bottom rail
an output array
an input array of n signal valu
a second intermedi array of signal valu
a pipelin processor of a radix-2 configur
a first intermedi array

a disk storag unit
the output of the de
the input of a de
the de algorithm
the bu of the disk storag unit
the bu of the central processor unit
the aid of the de algorithm data
a word width of 64 bit
a word width
a hard disk

a displac of an instruct code
the respect latch
the pipelin latch part
the pipeland stage
the oper stage in the pipelin latch part
the effect address calcul stage
processor with a respect latch
each stage between the effect address calcul stage
each respect latch in accord with the execut of instruct
data from the latch
an oper stage
an oper part
an effect address calcul stage
an effect address calcul part
a respect latch
a pipelin latch part

a display imag
transluc comput
the view space
the primit
the geometr primit of model in a scene among portion
the chunk in seri in a common depth buffer
object geometri in chunk
graphic object in a scene
graphic object
geometri for a chunk
chunk while primit for anoth chunk
chunk at a time
an effect form of compress becaus pixel fragment
a post process step
a minimum of memori

a display rang
these graphic subsystem
the least posit border of the textur map
the input pixel coordin
the input coordin
textur rang control
textur mode
textur applic
span processor within the scan convers subsystem
sitat
rang of the textur map
rang of a textur map
posit border of the textur map
pixel coordin in order
out of rang coordin
object data from a host comput
hardwar regist
form of textur
each span processor
comparison regist
a scan convers subsystem
a raster subsystem
a plural of imag engin
a geometri subsystem
a display subsystem
a display screen

a display synchron signal
variou resolut
variou memori configur
the resolut of input signal sample
synchron between a processor
single bit sample
signal sample in iter form
signal for display
other input signal sample
multi bit sample
hardwar for progress process of signal sample
filter display system
ccd memori
an iter configur
an input signal sample
address counter
a plural of refer sample
a pipelin configur
a hardwar configur
a filter display system

a distrbutor for the central execut pipelin unit of a central processor of a data
word align switche
unit of the central processor unit
unit of the central processor
the effect address of a target word
the collector unit
the central execut pipelin unit
the cach unit of the central processor unit
the a/q regist
some machin word
regist of the distributor
other sourc of signal
machin word
distributor of machin word between unit of a central processor
copi of machin word in key regist
an instruct by charact

a distributor
three dimension comput graphic apparatu
the prohibit of select
the processor modul
select of the data
pre draw process of the graphic data
output the graphic data
order in pipelin
geometr convers
command a output from the processor modul
a three dimension comput graphic apparatu
a state of prohibit of select
a plural of processor modul
a monitor

the binari valu
the absolut valu of the binari number
the absolut valu circuit
complement notat
bit level pipelin capabl

a divid circuit
divis in accord
bit level pipelin divid circuit
an array of bit level carri
adder with each carri
absolut valu bit level circuit

a dma control unit in the devic
the system via a bu
the system cpu
the servic inform
the devic coupl
tandem pipelin circuit element
system cpu
synchron with network commun process
synchron unit
servic signal transfer
servic inform
separ intern path
requir at the bu interfac
rel function autonomi
recurr time slot
plural stage pipelin
plural event
multipl logic circuit unit
memori unit storag space
link plural channel of a data commun network with memori
isdn digit voic
inform signal with the system cpu
each queue
each direct of commun
devic control inform
data telephon applic
data signal transfer
data link control
cpu compon of a data
commun data signal with system memori
coher bu oper
buffer memori unit
asynchron relat

the graphic processor
graphic microprocessor
user programm graphic coprocessor
thi bu architectur
the program rom
the host processor at all time
the host coprocessor
the graphic microprocessor
the graphic coprocessor
the game cartridg
special instruct
programm graphic processor for use in a video game system
point of view
own intern cach ram
individu pixel in the host video game system
gener regist
extern ram
extern memori system
bit map
a video game system
a remov extern memori unit for connect with a host inform
a read onli program memori
a pluggabl video game cartridg
a host video game system

a dma devic
the processor in a coprocessor mode
the number of paramet
the instruct in the instruct stream in a sequenti format
real time graphic function
processor mode
mode of execut
less time depend command
each display list packet
display list processor
display list packet
display list command packet in processor
differ code for differ locat
coprocessor mode of execut
certain command
an idl instruct within the instruct stream
a plural of command
a host cpu

a dma interfac
the slave comput
the operand data under control of a microprogram control section
the host main memori through the dma interfac
the host main memori
the arithmet logic oper
system with a slave comput
operand data into the slave comput
no intern random access memori
data regist a the sole operand store
an arithmet logic oper
an address of the host main memori
a slave comput
a host main memori
a host central process unit

a dma mode data
the host side
the host in order
pio data transfer on the peripher side
pci
memori data transfer into io data transfer
mass storag
fake
effici of io data transfer
dma mode data
data between host
an appropri dma request signal
address in the host memori space
a pio mode data
a dma timeout counter

a document distribut termin
supervisori cpu
memori system with access
larg volum of data
facsimil imag
control time share access
a peripher process control

a dot matrix ink
the separ print head
the pinch roller assembli
the paper transport system
the paper
the doubl side printer
tension roller assembli
simultan print on both side of a piec of paper
secur a sheet of paper
rigid plane with both side of the paper
rigid plane between the set of roller assembli
print head carriag assembli
pick up pinch roller assembli
mirror imag relationship
electron printer control circuitri
either side of the paper plane
bubble jet type desktop printer
both side of a sheet of paper
back page printer inform
a print head
a platen less paper transport system
a person comput by an rs-232 serial connector

a doubl buffer output regist
the special purpos
the second pass retravers
the graphic databas memori
the graphic databas
the geometri processor
the first pass
the databas memori
stack memori
pass
oper that cull out graphic data
graphic databas memori
geometri processor for graphic
doubl buffer input regist
display on a video display system
data from the databas memori
data from a three dimension mathemat format
a two dimension format
a second privat data
a microprogramm control system
a high speed arithmet process modul
a geometri process for use in a graphic
a first privat data

a doubl buffer techniqu
the second entri
the read data valu
the read buffer at the begin of each burst read access
the read buffer
the next burst access
the memori with time
the memori while the first entri store
the memori for the next transact
the i/o devic from the read buffer
the first entri
second entri
pipelin burst read
pipelin burst access in a semiconductor memori
oper in a semiconductor memori
gap less output data for consecut pipelin burst read transact
buffer entri store data for an entir burst transact
all read burst data
a read burst transact
a read buffer
a memori cycl time
a high bandwidth transfer rate between the second entri

a downstream circuit
wavefront of signal through a null convent sequenti circuit
wavefront
upstream circuit
the wavefront
the sequenti circuit
the downstream circuit
the asynchron regist
meaning data
asynchron regist
a wavefront
a varieti of architectur
a sequenti circuit
a null convent asynchron regist
a new wavefront

a drain instruct pipelin caus suspens
type of pipelin drain
thi dip instruct
the drain instruct pipelin
the actual store
previou store
pipelin drain
option
milli mode routin
milli mode onli instruct
interpret storag
interpret instruct in a pipelin
instruct buffer
an interpret storag
an interpret execut
all store request
addit control

a dram
the same clock cycl that the inform
output from an extern memori
microprocessor that pipelin memori request

a dram array
the dram array at a higher frequenc than the cpu
the dram array
the access latenc of the dram array
sequenc of column
row access
addit time
a synchron manner with respect
a self time asynchron manner
a second level cach memori
a higher frequenc than the frequenc of the cpu bu clock
a first level sram cach memori
a dram memori array a a second level cach memori in a comput system

a draw base web page editor
thi initi layout
the page in accord with the display element of the page
the link between page of the site
move display element
drag
true wysiwyg page for the site
thi layout
the site
the layout of each page in the site
the hierarchi of the site
html for each page of the site in accord with the display element of each page
hierarch structur editor for web site
display element
delet the appropri link between the page of the site a the user move
a web page
a structur editor
a layout for each page
the layout of the web page
the layout of a web page
html
draw base editor for web page
an initi layout for each page
a true wysiwyg page

a draw packet
the entir geometri object
the draw processor
scan interpol function
processor for a high perform
pixel into an interleav bank of a multipl bank
frame buffer
draw processor
direct port data through a direct port pipelin
dimension geometri object
a subset of pixel on a scan line
a draw processor for a graphic acceler

a dryer
time sequenc
the three way valv
the solenoid valv
the orient
the inlet
the ice
the high temperatur cold produc medium
the high pressur cold produc medium at a front portion with more potenti cool
the evapor
the dryer
the cold produc medium system
the cold produc medium low pressur return conduit
pressur sens devic
outlet
idl evapor by a solenoid valv
ice blockag
four way valv
evapor
dryer
drain
an automat drain valv
air pathway
air outlet
air dryer
a three way valv
a temperatur sens devic
a lower temperatur
a heat exchang i
a four way valv

a dual data cach microarchitectur
the instruct load data
the instruct issue unit
the first group of instruct
second group of instruct
an instruct issue unit
a second group of instruct
a second function unit
a plural of regist in a regist file
a load predict bit
a first group of instruct
a first function unit

a dual instruct decod
the second pipelin
the full instruct
the first pipelin
the execut of a second instruct in an instruct sequenc
the destin regist of a first instruct
subset of the complet instruct
subset of instruct
second pipelin
second instruct pipelin
principl of local
no regist depend between the instruct
microprocessor with apparatu for parallel execut of instruct
instruct in parallel within a single clock cycl
a regist depend checker

a dual interfac architectur
x/y
window move within the frame buffer
the host interfac
memori control reconfigur
independ memori control
graphic acceler with dual memori control
format without delay
execut of a previou command
either memori control
either extern bu
either direct
dual memori control
data align
buffer logic i
both memori control
an independ local bu
address multiplexor logic i
a second memori control
a frame buffer memori
a first memori control

a dual pipelin architectur for a system
unit normal vector
two dimension imag
three dimension surfac from variou view angle
the former pipelin
system for the simultan display
surgic procedur
surfac identif indicia
such system a magnet reson
oper dual pipelin
more intern surfac within a solid object
medic diagnost applic
each voxel element in accord
cube vector gener system
comput axial tomographi scanner
anoth pipelin
a graphic processor for the product

a dual port memori
thi memori
thi doubl buffer architectur
thi alloc
the top half of the memori
the preview access
the opposit bank of memori
the interfac between a numer processor
the bottom half
switch state
respect flag bit
read access
preview
ineffici at synchron point
doubl buffer preview mode
an addit address bit
addit bit tag the access
a preview access
a physic access
a logic access
a liter address within the full memori

a dual port memori element
the variou element of each node
the dsp element
sever process node
read/writ dual port memori
read oper by the dsp element
quarter
parallel process system for time divis multiplex data
opposit phase of clock
opposit phase of a frame clock
oper by the bu
each memori element
an exclus identif code
a synchron system
a memori element of anoth node
a memori control element

a dual system bu oper on a first protocol
transfer of command
the subrequestor
the interfac modul
interbu interfac modul
dual system buse
an interbu interfac modul
a subrequestor bu oper on a second protocol
a second group of requestor
a first group of requestor

a dummi instruct
dummi cycl for a number of cycl
control system in data processor
a micro program system of a pipelin control system

a dynam instruct
superscalar processor with a risc organ
out of order execut of condit code
instruct each cycl
function unit a depend
condit code depend instruct
comput organ
a short cycl time
a fast regist
a fast dispatch stack

a dynam memori
the global bit line
synchron dram cach
page access oper
memori array bit line
latch architectur
input/output connect
global bit line
cach memori in a comput

a dynam pipelin for a processor
the second arithmet element
the number of stage of a multipl stage pipelin
the input of a multipli
the first arithmet element
the arithmet element
the appropri number of stage
the alpha valu
simpler instruct
scaler valu
scalar valu
multipl latch stage
more latch stage
logic oper with other pixel valu
input pixel valu
extern sourc
anoth arithmet element
an arithmet element
alpha valu
alpha blend valu
alpha blend function
a first multiplex

a dynam system
the next comput
the matric in a pipelin manner
regular
rectangular systol array
pass through the array
fault toler kalman filter systol array
element in either configur
element for a regular filter
each pass through the processor array
anoth number m of observ compon
a plural of differ vector data oper set
a number n of differ state
a kalman filter
a four nearest neighbor network

a facsimil machin
the use of a pc
the modem with the telephon line
the convers modul
the apparatu convert such text data in first code
text data in a first code
such memori modul
signal strength
program card
other pc like devic
humid
hard disc
firmwar
virtual control word pair
virtual control word
the virtual control word
the size of the memori
the secondari control word memori
the firmwar
the content of that field
that single control word
secondari control word memori
no matter
field in the second virtual control word
field in the first virtual control word
field from both virtual control word
each field of each secondari virtual control word
don
control store space in a vlsi central processor
anoth virtual control word
a virtual set of secondari control word
a single control word
a primari control word memori
a plural of field
a field in the primari control word memori
facsimil scan line code
commun of text data in a first code between the convers modul
binari text data in a second code
ascii
an analog modul
a paramet

a failur
the trailer microprocessor
the point of failur of the shadow processor for further analysi
the output of the master
the differ in the intern state of the shadow processor
signal a the master
shadow processor
shadow pair of processor
shadow microprocessor
output those signal
number of cycl behind a master
a trailer microprocessor
a pipelin queue up bu activ from the shadow processor a number of cycl

a fast data accumul rate
time stamp data into time interv result
time stamp
time interv
third stage of the pipelin
these result
the third stage of the pipelin increment the appropri histogram bin in ram
the third pipelin stage read
the same bin
the previou event
the measur result
the limit
the histogram result
the histogram limit
the convers
substag
maximum limit
loop for the dual port ram
histogram
hardwar histogram gener
hardwar data processor
each time a new measur
circuit subtract
bin the measur
bin data
access conflict
a time interv trigger condit
a time interv data
a latch in the data

a fast fill method
the translate/decod stage
queue store control logic i
multipl micro instruct from the translat
micro instruct between the translat
hole
the regist stage of the pipelin
the present micro instruct
the descriptor compar logic compar operand
the descriptor compar logic
stage in the pipelin
regist gener micro instruct within a pipelin microprocessor
operand compare/releas
method for microinstrut sequenc in a pipelin processor
hole in the pipelin
gener micro instruct
descriptor compar
an operand of the present micro instruct
a pipelin releas
fill of translat instruct queue
bubble in the pipelin
an instruct regist within a pipelin processor
an instruct queue within a pipelin processor

a fast implement
the three to one alu oper
the three to one alu
the statu of three to one alu oper
the second instruct of the pair
the result of the oper of the first instruct
the presence/abs
the express
the critic path
scalabl instruct
machin alu statu predict
arithmet instruct pair
an implement scheme
alu statu determin apparatu
all combin
a three to one alu
a second instruct of a pair of instruct

a second portion
a first portion

thi arithmet logic unit
the sum of m
the multipli unit
the m other bit of the first input data
the l least signific bit of the product
the l
the dual product
plural independ processor oper
parallel oper
other bit
number of section
m other bit
input data buss
input arithmet unit
ident oper on independ section
embodi the m other bit
dual product from separ part of the input data
data buse of n bit each n
addit of dual product
a rotate/mask
a product from l bit
a n bit output

a fast load base regist algorithm
the user base regist of an instruct processor
the previou l
the new l
l
bdi field
an uncondit compar
an operand from a cach memori
a slow load base regist algorithm
a selector block
a new l field
a new bank descriptor index field
a load base regist user instruct

a fast resolut of condit branch instruct in a high perform superscalar processor
the overal branch
the logic circuitri facil
the first posit of the primari instruct buffer within the processor
the cycl boundari
such branche
resolut of a subset of condit branche
possibl mispredict for thi subset of condit branche
penalti
the oper control
the execut control data
regist in the execut unit
oper control data
number of pipelin stage
machin cycl for execut
an operand from a sourc
histori tabl base predict
effect mispredict penalti in a processor
averag branch resolut time

a fast sequenc
the slow sequenc
the necessari test
the fast sequenc
that sequenc
slow sequenc
slow microprogram sequenc

a fast trap
the trap number
the trap handler
space for a plural of instruct in each tabl entri
fast trap mechan for a microprocessor
addit handler code
a vector trap tabl i

a faster access time than the first memori
the first subset of object in a second memori
the first subset of object
the activ list
an activ list
a first subset

a faster decod
the same process cycl time
the principl element unit
the cycl time of the execut unit
sequenc of oper on instruct
risc type processor
risc type pipelin processor
oper of the instruct
n slower execut unit
n execut unit
least n
instruct from multipl program instruct set
each phase of the pipelin

a faster manner than the origin format
the system nullifi ani execut of a member instruct unit of a compound instruct upon occurr of possibl condit
the scalar execut of the base instruct of a scalar machin
the result seri
the interrelationship of member unit of the compound instruct with other instruct
the execut of the compound instruct format text
result of execut of the member instruct unit portion
logic unit of the instruct processor
instruct for parallel execut
control bit in the instruct format text
an instruct processor system
a seri of compound instruct with an instruct format text
a seri of base instruct of a scalar machin
a group of member instruct with compound in dictat tag

a faster multipl
the product sum oper unit
the product sum oper
the parallel bit data a an address
the number of time of multipl
th term data x
term input data x
subtract of 2-term data
set of intermedi data
processor of n term input data x
processor of n
output of the partial sum gener
input data x
inher characterist of coeffici of dct/idct
dct/idct processor
combin of an output of the product sum oper unit
bit data of the same figur of a set of data
a product sum oper of input data
a product sum oper for set of intermedi data
a partial sum gener
a partial sum
a one dimension invers discret cosin
a one dimension discret cosin

a fault recoveri process
the second test
the memori in a hierarch order in a master subordin relationship
the arithmet processor of each group
the alarm
system configur
supercomput
part of the memori
part of the arithmet processor
fault recoveri
an origin system configur
a test program
a plural of arithmet processor
a favor result

a fault recoveri system
the invoc of ani fault recoveri oper
the instruct stream of a multipl execut stage
the instruct flow
the fault recoveri oper
the execut of a specif stage upon occurr of a fault
suffici data from parallel execut stage in a central process unit for complet fault recoveri
overwrit log inform
each critic data item

a featur
thi document
the pipelin of the processor
the commun interfac
high bandwidth for larg block of data
fine grain commun
a second interfac

output voltag signal
input voltag signal
a neural network of a complex structur

a featur extract layer
two dimension layer
systol array of two dimension layer
neural network processor
layer
each layer within the network
dimension layer
a posit error
a pattern recognit
a mo analog circuit
a feed forward systol array

the pixel processor
the address control

a featur processor
second time
second sequenc
featur of object
dimension process of the data sequenc
data word of a data sequenc
data sequenc
data from the memori circuit in a plural of sequenc
data between the memori circuit
ani pixel processor
ani memori circuit
a plural of memori circuit

a feedback failur locat system
word by an error detect matrix
unreli media
transmiss media
the most like error word
the error correct system
reliabl memori
reed solomon error correct code
messag word by a gener matrix
high rate with minimum delay
fiber
error correct system for reed solomon code
encod
code word
byte parallel system
byte failur locat inform
ani type of parallel data storag
an arbitrari level

a feedback loop process
the second input at the time
the other end of the circular pipelin
the oper of the oper result
the oper execut unit
the input data packet
synchron of the oper execut of the oper
result of the oper execut unit
oper with respect
hold
feedback loop process
end of a circular pipelin
an input of a data packet
a synchron control unit
a subsequ feedback loop process
a feedback loop process instruct

a feedback path
view independ radiat calcul
the surfac with grid cell
the result of the form factor
the radios
the radiat sourc
the imag plane
the ident of the polygon in the environ
the form factor for radios techniqu
the form factor calcul
the face of the cube
the depth of surfac from the viewer
the depth from the sourc
the cube
the cpu memori
surfac in the environ
surfac from anoth surfac
scan convers hardwar
ray trace calcul by sever order of magnitud
radiat imag
mirror posit of the viewer
light buffer
grid cell
everi view of the same environ
each radiat sourc
each grid cell
all other surfac in the environ
a novel ray trace techniqu
a light buffer in the form of a cube
a hemi cube i
a graphic pipelin

a feedback storag unit
the output framestor
the feedback storag unit while complet composit
the feedback storag unit
the complet composit
recurs techniqu
real time video product
partial composit
an output framestor
a real time video product techniqu
a preview video
a length of mani frame the complet composit

a feedback type neural network
weight data
the size of the circuit
the prsent invent
the number of the wire
the neuron comput
the neural network
the necessari weight data from the weight memori
neurocomput with analog
necessari control data from a control pattern memori under the control of micro sequenc
input from an analog
anp in differ layer
anp
an analogu neuron processor
an analog signal bu through a nonlinear circuit
a time division analog input
a single analog
a plural of anp in a single layer
a plural of anp
a parallel oper in the same time period
a parallel oper in a pipelin manner
a neuron comput with a high practic
a neuron comput

a few exclus or gate
the stage regist
the signatur pattern
the misr at the end of the test sequenc
the misr at the end of the sequenc
multipl input shift regist
a uniqu signatur pattern
a uniqu sequenti test sequenc of instruct
a uniqu sequenti input pattern
a particular test sequenc

a fft
the storag part
storag part
oper with the output
invers fft
fft oper
feed back read out data
a third storag part
a storag part
a second storag part
a first storag part

a fiber optic bundle
visual refer the locat of the problem
these valv
the system processor
the loss
the light detector
the fiber optic light
the circuitri within the detector
the center of the valv handle
memori circuit
loss of current flow
intermitt faulti loop
ga zone valv emerg alarm system
fals alarm
an open circuit
an alarm condit
a system annunci
a plural of zone valv
a number of reason
a light detector
a floor control panel

a fifo buffer
the util of a vertic instruct
the remaind of the array process circuitri
serial to parallel convert
function number

a fifo memori
plural storag
intermedi read
fifo memori
data process system
anoth fifo memori
anoth alu
a set of data signal from an alu
a plural of fifo memori

a fifo pipelin bu
wavefront of data an null across the bu transmiss line
null convent storag regist at the transmitt port
null convent storag regist at the receiv port
each null convent transmitt port propag
a plural of null convent transmitt
a plural of null convent receiv port
a plural of bu transmiss
a pipelin bu
a null convent receiv port

permut
the sample valu

a filter
the signal process circuitri
the signal process circuit multiplex the intermedi output
the logarithm filter
the filter stage
the electr represent of the filter paramet
that filter stage with a signal from an output of anoth filter stage
signal convers
output in cascad
electron filter
an electron filter
aid
u
the u
space administr
respect circuit a govern support thi invent
research grant
nation aeronaut
govern support under veteran administr contract va kv 674p857
govern
transform rule
the circu background of the invent the u
the activ of a plural of processor
spatial local
physic space
non exclus right in thi invent
multidimension cellular data array
memori organ
each subdivis
data blind data movement upon the data bit
data array comput
darpa
an iter updat oper upon data bit
a physic space
certain right in thi invent
a seri of filter stage with input
a logarithm filter
other electron filter
respect circuit
electroacoust system
electr represent of filter paramet
an intermedi output
a set of filter sum signal
a logarithm prefilt
a logarithm postfilt
a filter sum

a filter output
the wl sample valu
the composit signal
set of wl sample valu
sample valu
respiratori signal
method filter an artifact from a composit signal
electromyogram
electrogram
electrogastrogram
electroencephalogram
electrocardiogram
each permut
digit system
artifact from signal
artifact from composit signal

a filter section
real time render on a display
quadrat polynomi fragment
qpf
pipelin for real time object
part of a real time object
fragment of two dimension graphic object
an interlac correct section
a pre calcul section

a final area
the structur in the hierarchi
the pick stack
the machin state memori
state descript
rapid pick identif
rapid copy of row
primit machin state identif
primit echo machin storag
machin state of pickabl primit oper through the use of a pick stack
machin state inform
machin state for variou structur level in the hierarchi
hierarch graphic structur
function for a pipelin graphic system
element from the stack a structur
a video ram
a second area
a first area of the machin state memori

a final branch outcom
the retir stage
the oldest instruct in the out of order unit
the final branch outcom
the branch predict stage
the branch execut stage
step of branch recoveri process
stage verifi all branch predict
stage branch instruct resolut system
restart the processor
outcom of branch instruct within an instruct stream
final branch target address
dual predict branch system
branch predict for branche
all branch instruct
a second stage decod
a first stage of the branch instruct resolut system
a final branch target address
a final branch resolut stage

variabl length comput instruct from a stream of complex instruct
the set of instruct byte
the next instruct detector
the first instruct byte
the end of the first instruct
shifter
set of instruct byte
output the next instruct
instruct byte of individu one of the complex instruct
instruct byte in the stream of complex instruct
an extract shifter
a variabl number of instruct byte
a risc processor core
a portion of the stream of complex instruct
a next instruct detector

a final bucket
non nativ instruct
nativ instruct

a final complet result
the total number of clock cycl
the redund intermedi form
the redund form
the perform of the processor
redund intermedi data form
processor with architectur
a redund intermedi form of a result

a final jump predict
the valu of the jump paramet in the instruct
the outcom of a condit jump instruct
the jump predict
the histori of the outcom
previou instanc of execut of those instruct
particular use
correct mechan
condit jump instruct
a jump predict circuit

a final logic column
tripl logic column form
time critic input signal
those input signal
the time the critic input signal i
the revers of the state of the critic input signal
the output node
the middle portion of each logic column
the critic time requir
the critic input
the condit of the output
readi for the critic input condit
lower portion of the logic column
lower portion of each logic column
embodi the circuit of thi invent
circuitri in a manner
chang in the state of the critic input signal
chang in some critic input signal
advanc
underflow
the type of oper
the predict method
the indic
the handl of the except
the expon field of the operand of the comput in a manner
the event the comput
that method
that combin
substract
oper until complet of the comput
an indic of the possibl of the comput
an indic of the comput
a minimum of effort
a low potenti sourc

a final result
the mantissa of the intermedi result
the float point regist
the addend align amount
prenorm of intermedi result
overlay
denorm of float point result
an underflow condit
an expon
adder operand
a float point instruct

a final result i
the symmetri of the coeffici
the ident coeffici
ident counterpart
fir coeffici
each pair of data point
each coeffici
data point
advantag of symmetr fir coeffici of fir filter in audio equip
a finit impuls respons filter processor

a final stage reintegr
version of the origin imag data
the origin imag data
present format
preprocessor
parallel encod
overal process speed
imag stream
imag data into a plural of stream
imag data encoder/decod system
extern transfer
each stream
decod unit
decod system
decod architectur
constitu
volum of sample into the probe chromatograph
vessel
the sourc pipelin
the quantiti of the respect constitu
the process stream
the probe chromatograph apparatu i
probe chromatograph
chromatograph
an analyz mechan
a probe chromatograph
a pipe nipple into the fluid flow
composit form
an imag data encod

a finit number of uniqu identifi
thi issue
magnitud
execut of a program within the data
counterpart
an uniqu identifi
an age relationship between instruct
an age relationship
a uniqu identifi

a finit state machin
wasmp
the present intern state
the pipelin decod
the fsm
the concurr applic
output binari sourc signal
low order pairwis
k component/k candid next integ valu control paramet
k compon vector represent
k candid next control paramet
interact signal relat
finit state machin
finit number of string
fifo rissanen/langdon arithmet string code of binari sourc
digit of a decod set
continu flow through a pipelin processor
bit from success arithmet code bit
a k way select from k candid next intern state
a k compon present integ valu control paramet

a first accumul buffer
z inform
the pixel engin pipelin
the control logic store
system memori into a load data queue
second accumul buffer
read request in the command queue
pixel inform
pixel engin pipelin for a 3d graphic acceler
graphic instruct from a graphic processor
graphic inform
extract instruct
data into a read data queue
data from the pixel engin
commun pixel inform between a graphic processor
a store buffer for subsequ write
a stage of the pixel engin from the read data queue in accord with the extract instruct
a second accumul buffer
a read request queue
a portion of the read request
a pixel engin pipelin
a load request queue

a first address gener logic i
the second group of the pointer regist
the second group of data regist
the second address gener logic i
the read circuit
the first group of the data regist
the first address gener logic servic
the execut of a second instruct
the exchang instruct in parallel with other instruct in the data
the data regist
the address of the second group of the data regist
the address of the first group of the data regist
set of pointer tabl address
point instruct the second instruct
point instruct in parallel
point instruct a second address gener logic i
parallel with the first instruct
apparaut for parallel exchang oper
an exchang of content
an exchang instruct
an exchang circuit
a second group of the pointer regist for the address of a second group of the data regist
a read circuit
a pointer tabl
a plural of pointer regist
a plural of data regist
a first group of the pointer regist for the address of a first group of the data regist

a first algorithm
trainabl
second predictor
outcom of branche
more predictor
instruct outcom
a second compon predictor
a second algorithm
a predictor
a predict of the action from the predictor
a predict of an action
a first compon predictor

a first arbit element
the second arbit element
the next grant
the first arbit element
the delay in the access of user
the arbit of the present invent
the arbit circuit of the present invent
subsequ request from the first user
second arbit element
other user
other embodi
more request signal
fourth arbit element
a second arbit element
a grant
a first user access

a first arithmet unit
trigonometr function arithmet processor
m step
a trigonometr function arithmet processor
a sequenc of number
a pseudoremaind
a pseudo divis oper

a first aspect
the stage of the microcod instruct
the second control storag
the machin instruct
the first step of the machin instruct
the first step of a branch target machin instruct of a branch machin instruct
the first stage of the second step
the first control storag
retriev control
microcod instruct at the second stage of the first step of the machin instruct
microcod instruct a a plural of step
each step
control system in an inform
a second control storag
a second aspect
a process of the branch machin instruct
a first step of the machin instruct
a first control storag

a first binari valu
thi process proceed from the msb
the valu of the msb
the valu of the bit of interest
the valu of each bit
the sort select code
the sort select
the resolut of the data valu
the process by all bit stage
the data valu by bit posit
that data
relationship between the valu of the bit for the bit posit of interest
possibl candid for the data
lesser signific bit
digit hardwar select filter
decid upon bit valu
bit valu
bit modifi
a sort select control code
a sort select
a set of n data valu
a second binari valu
a plural n
a plural m of bit

a first bit clock cycl latenc
vdram data
the sam
the primari latch
the first bit of the vdram data
no latenc pipelin
a video dram
a secondari output port of the memori
a primari latch
a pipelin techniqu

a first bitwis logic oper on bit signal
third regist at the begin of each clock period
third regist
the third regist
the second regist
the plural of second gate
the output of the second gate at the end of each clock period
the output of the second gate
the first regist
the first gate in a bitwis manner
second set of vector element
second regist
second gate
receipt a pair of vector element
parallel vector logic oper system
pair on the same sequenti clock
initi data
back circuit on sequenti clock period each clock period
back circuit
a vector logic oper apparatu
a second bitwis logic oper on bit signal
a plural of second gate
a plural of first gate
a pair of the first vector element

a first branch in the pipelin
the state of a circuit element in a faulti circuit if the fault
the memori block
the function of the gate
test vector for a circuit
such record
interconnect in the circuit
faulti version of the circuit in a comput simul
faulti circuit
concurr fault simul of circuit with both logic element
candid test vector
both logic gate
a second branch
a multiprocessor in a pipelin configur
a memori record

a first bu cycl command/id inform
whereon command/id inform
the second group of signal line
the first group of signal line while the address
the first group of signal line
the dual function of the first group of signal line
the bu inform
the bu connect with suffici time
the address a full bu cycl befor the data
other bu connect
multipl word data return from a system memori
data signal line path
command/id
circuit element
address inform through the system
a subsequ bu cycl
a second group of signal line
a particular word of data
a first group of signal line

a first buffer storag unit in a central process unit
the second buffer storag unit
the first buffer storag unit
the first bu
secondari cach memori
devic output the address
devic obtain a right
an output of the control unit
an output control unit in the memori
an idl state if the second buffer storag unit
a second buffer storag unit
a request for access

a first cach memori
thi attempt
the second cach memori
the school cach memori
the first cach memori data
the first cach memori
the execut of a first instruct data
perform in a multi level cach system by the use
execut of the first instruct
each cach memori
data integr in the system memori
a subset of data in the system memori
a subset of data in the second cach memori
a second cach memori

a first case
the use of the regist
the plural of byte
extern peripher devic
circuit pin
ani extern devic
a varieti of memori devic
a user greater function flexibl without softwar intervent
a user great flexibl
a second instanc
a function of the byte
a function of a plural of byte

a first class of macroinstruct
the second class of macroinstruct
the out of order processor
the execut of the microinstruct
the execut of certain i/o
memori oper in an out of order processor
execut of microinstruct
apparatu disabl
a second class of macroinstruct

a first clock cycl
the statu data
the output of the interfac circuit
the interfac circuit
the extern circuit
statu data
non prioriti inform
either prioriti
both prioriti
an interfac circuit
a prioriti inform path
a non prioriti inform path

a first clock period
the second clock period
the first address
subsequ clock period
slower speed memori
signal caus the extern memori devic
pipelin the second access
memori access type
effici access
data from an extern memori devic
complet of the first access
activ the chip
activ a chip
a third clock period
a memori devic with a slow memori core
a first memori access
a first data element

a first coeffici in a first regist
the third data
the second coeffici
the result in the fourth regist
the result in a fourth regist
the product of the second coeffici
the product of the first coeffici
the product in a third regist stage
the input signal i
the fourth data
the first coeffici in a second regist stage
the first coeffici
sixth data valu in the first regist stage
second data valu
fourth data valu into the second regist stage
fourth data valu in the first regist stage
fourier transform of an input
a first regist stage of a subsequ process stage

a first compar
the vector operand
the operand counter of each operand with the content of the maximum number regist of each operand with respect
the operand counter
the maximum number of element
second compar
part of the output
operand counter
operand address regist of ech operand in respons
maximum number regist
element of a plural of vector operand
a second compar

a first condit code regist
the second condit code regist
the result of the current instruct execut
the processor state result from the execut of instruct
the first condit code regist
the first condit code
the condit code state
second condit code regist
control of a central processor in respons
ani condit code state

a first control
the transfer request signal chang
the statu of a data
the second control signal i
the reset input
the prior art d
the path of data
the output of the nand gate
the flip flop output
request signal i
request signal chang
parasit oscil
input nand gate
inactiv the first control
hand shake type data
anoth circuit
an input of the nand gate
an inact statu
a second control
a nand gate
a hand shake type control circuit

a first counter
a second counter

a first data word
transact in thi manner
the interfac of memori devic
data from the memori array
address from the sourc devic
address from a sourc devic over a first bu on a first clock cycl
a read transact
a later clock cycl

a first delay path
therebetween
the redund time signal a activ
the other a inact
the inact redund time
temperatur compens
signal design
second redund time signal
redund time signal
phase relationship therebetween
multipl time subsystem
method for clock align
inact output
inact
an effect of temperatur chang on the delay path
a telecommun system
a second output
a second delay path
a programm delay valu
a first output

a first differ
the second operand from the first operand
the second differ
the manhattan distanc
the first differ
the absolut valu of the differ between the first operand
the absolut valu of a differ
a second differ
a first operand from a second operand

a first direct
the sparc instruct
the revers direct
the comparison circuit
the answer
multipl address regist orient instruct set
instruct of the type
flow in the other direct
execut of the present instruct
differ stage in the pipelin
differ instruct
counterflow pipelin processor with instruct
comparison circuit in each stage of the pipelin permit instruct
commun in the pipelin
both way between adjac stage

a first durat if the next instruct
variou type of except condit in the cpu
the statu signal for respect durat for each such type
the statu logic
the execut of the next instruct
statu output
statu logic
puls width
chang in the flow of instruct
an intern instruct pipelin
a second durat if an except condit
a puls width
a normal sequenc

a first execut
the second e unit
the plural instruct
the instruct into a plural of stage
the first e unit
second e unit
second circuit
part of the plural instruct
oper unit
oper circuit
inform of the instruct
execut of oper stage
execut of oper
data in synchron with the end of oper
a second e unit
a queue of data
a plural of instruct in a pipelin mode

a first execut processor
the first kind of instruct
the control issue
second execut processor
parallel with each other
microprogram control
instruct in a program sequenc
a second kind of instruct
a second execut processor
a first kind of instruct

a first function
the vector processor of the present invent
the oper by the second function
the index valu
the index set
the first function a a data
the first function
the deterior of the effici of pipelin
the calcul of array data
express
differ oper content
continu oper vector processor
continu calcul of a plural
advanc a separ index
a second function

a first imag
walk through render system
view posit
system for walk through applic
system for a walk through imag
an imag base represent of a scene
a second imag
a geometri base render approach

a first input of each sens amplifi in the first stage
the second input of the sens amplifi in the first stage
the respect second input of each sens amplifi in the second stage
the refer voltag
the other sens amplifi in the first stage
the other data signal
the oper of the second stage
the mode control circuit coupl an output
the mode control circuit coupl a refer voltag
the mode control circuit coupl a data
the complimentari output signal from each sens amplifi in the first stage
the complimentari data signal
sens amplifi stage
sens amplifi for complement
no complementari data signal
ident sens amplifi circuit
each sens amplifi stage
differenti input
a sens amplifi
a respect sens amplifi in the first stage
a respect second input of each sens amplifi in the second stage
a respect second input of each sens amplifi in the first stage
a respect data
a mode control circuit coupl
a first input of each sens amplifi in the second stage

a first instruct from the program memori
the program memori in respons
the program control unit
the control signal for use
separ program
separ data memori
embodi of the method of the invent
digit signal process method
data valu from the data memori
data from the program memori in respons
address signal in respons
a sequenc of the instruct
a second portion of the data
a second instruct from the program memori
a read of data from the data memori in respons
a first portion of the data

instruct in a processor
version of the invent
sourc inform

a first instruct into a second instruct in a processor
the method searche
the method first searche for the second instruct
the first instruct via the second instruct
probabl
point instruct in a processor
point instruct if the sourc address
execut by the execut unit
aspect of the method
a sourc address

a first instruct within a specul execut path
the resourc counter
the multipl execut unit
the first counter
the alloc of resourc within a processor
support specul execut of instruct
resourc alloc within a processor
complet of a particular instruct among the number of instruct
an instruct among the plural of instruct
a valu of the second counter
a valu of the first counter
a resourc counter
a refut of the specul execut path
a number of the plural of resourc

a first locat
the same first locat
the same first instruct
the processor of the array
the number of processor in the array
some processor
each processor into a plural
addit processor in a simd parallel processor array
addit processor in a simd comput
a simd comput in thi fashion
a separ processor
a problem

a first logic valu
the valu of the updat bit posit
the valu of the updat bit
the valu of the statu bit posit
the last stage of the pipelin
the abov step
that stage of the pipelin
statu inform in a comput
an updat bit posit
all trap
addit pipelin state
a statu bit posit
a next stage of the pipelin
a next advanc of the pipelin
a first oper

matrix multipli
matric

a first matrix with a second matrix
the final product matrix
the element of the product matrix of that stage
parallel with the other pipelin of that stage
each pipelin within a stage
each column of the product matrix
an intermedi product matrix
a third matrix with the intermedi product matrix
a first multipl stage

a first meaning signal state
third signal state
the threshold number of input signal
the threshold
the third state
the number of the input signal in the meaning state
the meaning state
second signal state
output null convent signal
null in respons
circuit trigger chang of the output signal state
all input signal
a plural of physic input signal line
a null signal state
a null convent logic element

a first meaning valu
the total number of input
the threshold number
the number of meaning input valu
the number of meaning input data valu
the gate
other process function
no data signific
meaning signal valu
hysteresi
group of element
a plural of null convent signal
a null valu
a null output
a null convent logic system
a meaning output valu
a meaning output data

a first memori area
variabl length instruct in a superscalar
the second memori area
the number of data word in the longest permiss instruct
the initi data word of a variabl length instruct
the indic a delimit of the sequenc of to be decod instruct
the first memori area
sequenti to be decod instruct
sequenti address in a main memori
sequenc of data word
plural indic
multipl indic
more non overlap subsequ of the sequenc of data word
each subsequ of data word
each instruct of a variabl length instruct
each indic
each data word of the data line
data line
a sequenc of data word
a separ instruct
a second memori area

macro instruct
a macro instruct
the macro instruct

a first micro instruct
the same locat in memori
the load micro instruct
the destin of the result
the alu store
store indicia
oper store micro instruct
memori storag micro instruct
an oper micro instruct
an alu store
a store suffix
a load micro instruct

a first microword of a routin
the second output of the rom
the legal instruct
the illeg instruct
the first output of the rom
opcod decod
no output from the decod
no output
legal instruct oper code
legal instruct opcod
an opcod decod
an illeg instruct
a plural of second output in respons
a plural of output signal from decod
a plural of output signal
a legal instruct
a first output in respons

dynam resourc alloc
more task microinstruct
more task
each task
each high level instruct
a microinstruct level

a first number
the first number
the content of the last regist
the content of the indic regist
the content of the counter
the coeffici of the syndrom
set of regist r
set of regist q
error in reed solomon decod
degree
the same physic hardwar
the execut of a plural of microinstruct
an indic regist
a reed solomon error correct system

a first one dimension dct processor
two dimension discret cosin
two dimension dct of the input data matrix
the two dimension discret cosin transform
the transpos
the amount of memori capac
rom size
partial sum
part of a video bandwidth
other two dimension data
matrix from the first processor
column of vector inner product
block of video pixel
an entir row
a transposit memori
a second one dimension dct processor of similar circuitri

a first oper execut section
the second regist group
the oper execut section
the first regist group
no memori operand
instruct pipelin microprocessor
data a the result of a look forward execut of instruct
an oper execut section
an instruct pipelin type microprocessor
a third oper execut section
a second regist group
a second oper execut section
a result of execut by the oper execut section in the form of a flow of program
a first regist group

a first oper of select addit
set of input data from a row
parallel architectur
output data valu
order of the input data
order of input data
larg core memori
input data valu
each pass stage
dimension matrix of such input data valu
dimension fast fourier
an input shuffle arrang
an array of input data valu
a transpos of a matrix
a shuffle oper
a second oper of select multipl by an exponenti multipli
a plural of ident switch circuit
a novel architectur
a new fast fourier

a first oper result
the third oper result
the second oper result on the galoi field
the second oper result
the first oper result
element of the galoi field
element of a galoi field
circuit of a galoi field
circuit for galoi
an oper of the galoi field
an addit of the first oper result
a third oper result
a second oper result
a flag decis circuit

a first packet of data
time into the system
the second packet of data
the first packet of data
pipelin parallel process architectur
a second packet of data

a first phase
the tag regist in step
tag data
subsequ sequenc of instruct
pipelin control system for an execut section of a pipelin comput with multipl select control regist in an address control stage
a second phase
a pipelin control system for a comput
a flow
a first sequenc of instruct in order

a first pipe stage
the total shift oper
the shift unit
shifter element with pariti predict
pariti predict
oper into partial shift
final
differ pipelin
a second pipe stage

a first polynomi signal gener
the re time error
the plural of delay
the paiir filter
the first polynomi valu
the first polynomi signal gener
the adapt section
set of weight signal
second input signal
look ahead process on the second input
first polynomi weight
an adapt section
adapt infinit impuls respons
adapt iir filter
a plural of delay
a non adapt section
a first polynomi valu

a first portion of a plural of gener purpos i/o pin
the possibl oper mode
multipl oper mode
intern memori storag element
extern memori storag element
circuit structur
addit extern i/o circuitri
a third possibl oper mode
a second possibl oper mode
a second portion of the gener purpos i/o pin
a plural of possibl oper mode
a part
a first possibl oper mode

execut circuitri for execut
the execut circuitri

a first power mode
power consumpt in an electron circuit
n number of instruct
dispatch circuitri
cycl of the dispatch circuitri
an integ number

a first prefetch storag circuit
the first prefetch storag circuit
single cach memori line a either branch target entri
prefetch instruct queue
multipl instruct prefetch storag circuit
cach memori system
branch target instruct byte
a second prefetch storag circuit
a processor with a branch target cach

a first project of the object with respect
those locat
the refer frame of the acquisit equip
the extrema with respect
the axi
refer frame
project locat
extrema of the object
extrema of object
extrema of an object with respect
an axi of a coordina system

a first rang of address
the subsequ datum
the statu regist
the n low order bit of the subsequ datum
the n low order bit of address
the first rang of address
the address of a subsequ datum
plural of data
m high order bit
high order bit within a regist
an updat
an address bit width
address of instruct
a subsequ datum

a first read circuit
the vector element
the search rang
the element of the first vector
logic oper on the element of the second vector
element of a second vector
each compar
a second read circuit
a search request
a search rang
a portion of the element of the first vector read by the first read circuit
a first vector

a first regist
vga
tv
the vga
the variabl line rate
the total number of pixel in a line
the total number of pixel in a displayabl line
the scan convert
the period of time
the horizont rate
the digit to analog convert
the asymmetri of tv standard
svga graphic data
portabl pc
pal tv data
output ntsc
line with fewer pixel
line buffer with variabl horizont line rate
less time
graphic control
everi second frame for svga convers
either crt pixel convers
crt
an extra horizont line
an extern tv
an extern ntsc/pal tv
a scan convert
a portabl comput
a flat panel display

a first row of dram cell in the memori circuit in respons
transistor dram cell
the select circuit access the second row
the second row of cell
the dram cell in the first row
the dram cell
embodi of the circuit
dram cell in a memori devic
an inact state control
an activ control
a second row of dram cell in the memori circuit in respons

a first shader
valu in a comput
third shade paramet
the pixel interpol valu
the first shade valu for the pixel
second shade valu for the pixel
second shade paramet
interpol of pixel
direct fashion
a second shader
a pixel interpol valu from an object descript
a particular pixel

a first shift regist
transform in digit imag
the serial signal i
the segment
the represent
the origin digit signal
the logic unit
the first shift regist
specif function of particular interest
signal segment
a second shift regist
a plural of logic function

a first signal i
the front end of the processor
the front end
that execut
resourc via exclus access control
resourc in respons
processor implement method
next instruct
atom unit
an atom instruct
a second signal i

a first sourc
the second result
the multimedia input devic
system for signal process
set of valu
result in the accumul
multipli add oper
intermedi result
a second sourc
a multimedia input devic

a first stage of the processor
the variou stage
the variou buse
the quick simultan transfer of data
the necessari buse
second data memori
respect address gener
neuron network
effici process
each other through the use of independ buse
common oper
bu coupl
an i/o interfac
a uniqu bu architectur
a program address gener

a first state
the number of processor cycl
the instruct statu indic
that execut of the instruct
instruct progress within a data
instruct execut within a processor
an instruct statu indic
an event occurr
a statu of an instruct
a reason code indic

a first subsequ processor cycl
the statu signal with the specif condit inform
the second subsequ processor cycl
the first subsequ processor cycl
the condit instruct
section oper
perform of a specif condit test
other section of the digit processor
anoth instruct word
a statu signal
a single condit instruct
a second subsequ processor cycl

a first switch circuit
third switch circuit
third control signal
thi pipelin processor
the signal gener of an execut control circuit
the second switch circuit
the precharg period
the execut control circuit
termin of the accumul regist
second data buse
input termin of the accumul regist through a second switch circuit
fourth control signal
data on the first data
an accumul regist
a third switch circuit
a fourth control

a first vector regist
the vector shift function unit
the valu of the shift count
the operand by an amount
shift count for each operand
shift count
number of vector regist element
element of a vector regist
differ word locat of anoth vector regist
amount in a single process
a vector supercomput processor
a vector shift function unit
a third vector regist
a set of shift count
a set of operand
a second vector regist

a first-in first out memori
the second circuit
the orderli flow of data in accord with the architectur of the microprocessor
the float point data
the first-in first out memori in the event of a cach
the first-in first out memori
point data in a microprocessor
data in a pipelin manner
data from an extern memori system
coupl data from the cach
an onchip data cach
a float point unit
a float point data

a flag group
the instruct through the pipelin
system with regist
flag group
conflict in a pipelin
a flag group memori

a flag operand
the specul state of the microprocessor
the real state of the microprocessor
the real state of flag
the perform of the microprocessor with respect
the flag storag area in place of that flag until the actual flag valu
the flag storag area
the earlier execut of branch instruct
flag tag
flag operand
a flag tag
a flag storag area

a flash memori compon
non volatil code

a flexibl
wavelet
the video commun
the comput vision field
high oper
a wavelet
a pipelin with a bit unit
a low complex in circuit

a flight
the arithmet pipelin processor
comput graphic
arithmet pipelin for imag
an equat of the form
a group of board

a float point oper instruct
the float point oper instruct
kind of instruct
integ oper with except
fpu
float point oper instruct
everi end of the instruct
effect process of the fpu except
bit in a psw
an integ oper instruct
a mode that the fpu except

a float point stack exchang instruct
the swap data
the stack operand
the pipelin befor either instruct
the pipelin a separ pipelin flow
the exchang instruct
the exchang
instruct by operand translat
halv
each half
both halv of the exchang instruct
a translat circuit
a stack regist swap
a separ exchang instruct
a regist by absolut number

a flow control bit
thi flow control
the transfer of instruct byte from a prefetch buffer
the transfer of instruct byte from a current prefetch block
the prefetch clock
the next prefetch block
the flow control bit
the complex
instruct byte in the prefetch buffer
flow control bit
flow control
each prefetch block
cof instruct
chang of flow within the code stream
chang of flow instruct

a flow rate
tube
the magnet field gener
the fluid level
the flow rate calcul
the flow rate
the electromagnet flowmet
magnet field gener
fluid at an end portion
fluid
the percentag of the compon
use of nmr analysi
total flow meter
the time between puls in a seri
the fid peak amplitud
the cut
the analysi
soil compon
seri of puls
sample of the compon
result of these measur
rapid puls nmr
puls seri
other hydrocarbon in a fluid flow
oil for exampl
oil
nmr emiss
meter
matter
fid peak
differ level of random molecular motion
constitu part of molecul
compon of a multiphas fluid
atom speci
an accur measur of flow rate
advantag of the differ spin relax time
accur measur
a real time basi in the field
flow rate output
electromot forc
electromagnet flowmet
earth electrod
an electromagnet flowmet
an axial direct
a point electrod
a lower portion
a fluid level
a flow rate of fluid

a flow restrict in the pipelin
water content of crude oil
the variou compon
the temperatur of the mixtur in the flow restrict
the rel proport of the compon of the mixtur
the radiat
the ga
the flow restrict
set of signal
separ radiat energi for each compon
mass flowrat valu
accur valu of flowrat
a radioact sourc

a flush regist
the request address
the replac buffer
the process of the request
the invalid process
the address in a replac buffer
fault correct
an address regist until the invalid
an address array of a store in cach memori
an address array
a replac control

thread descriptor
the instruct pointer point
the frame pointer point
a thread descriptor storag
a frame pointer
a frame of memori locat that the next instruct

a fork instruct
token
token data
the state field
the schedul of execut of instruct
the activ frame memori locat
system with operand
other inform about an activ frame memori locat
operand for instruct
non associ portion of memori
data object
an interconnect network
an activ frame memori locat
activ frame
a state field
the current thread descriptor
processor with fork
multipl thread of execut
a start instruct on a first processor
a single thread descriptor

a forward
the capac
techniqu on a data
sequenti processor
pattern of data
less memori
fewer clock cycl than neural network
feed forward neural network
an inher similar between the flow of inform in the brain
a result of thi invent

a forward process
the signal process apparatu i
the forward process
neuron model cell
each neuron model cell
a hierarch neural network

a four deep pipelin regist
the state of signal
the combin of a funnel shifter
separ regist
form a configur pipelin
certain result
a number of multiplex
a merg logic unit

a fourier transform of an input
the transform coeffici
the product with the correct sign
the normal domain
the last signal data
the last product
respect sum
respect product a addit in the logarithm domain
parallel signal processor
method for fourier transform
an accumul of the respect process element
all complex output signal data point

a fraction of the nomin clock while execut
thermal threshold
the thermal condit
the rate of acceler of a function unit
the queue activ rate
the provis of circuitri
the nomin clock rate
the clock rate
the clock frequenc
system for thermal overload detect
stall threshold
stall mechan at the boundari of each stage in the pipe
protect for a processor
prevent
method for thermal overload detect
maximum potenti for the vast major
full throttle
execut life
circuit processor
an idl queue
a stepwis fashion
a short period
a queue activ rise time detector

a fractur point of a pipe line network
way of a plural of the special purpos
the rang of the set
the pressur
the normal consumpt condit
the fractur point
the extent of a practic toler limit
the exist of fractur on a certain joint in the set
the case that a rang of a set
system for such network
refer data of flow rate
pipe line characterist
local data in the pipe line network
fractur point of pipe line network
flow continu requir in a fractur accid
distribut characterist of extraordinari pressur variat
data of the flow rate
applic order of individu one of the group
accord with data condit of the pipe line network
abnorm joint through a comparison between result of the numer simul
abnorm joint
a numer simul
a larg scale water distribut pipe line network

a fragment buffer
the stream of geometr primit
the other pixel buffer with pixel data for the next chunk
the edg equat paramet from the set up processor
pixel record
pixel buffer while the pixel engin
pixel address
fragment record
fragment list
fragment buffer
edg equat paramet
doubl buffer pixel buffer store pixel record
control storag of pixel
chunk
an anti alias engin
a stream of geometr primit
a set up processor in the chip
a scan convert processor

a frame buffer interfac
the vblank command
the display system for display
that buffer
synchron with data
serial render system
all other process
all other access throughout the system
a specif buffer portion
a serial render system

a frequenc domain fast fourier transform
very-high speed frequenc domain fft
the output line valu
the locat in the memori
the input line
the coneolut of sample
the address input port
frequenc bin output line
an output line
address input port
a plural of input line

a fualt toler comput system
digit data processor with high reliabl

a full control circuit
the rel reaction
the next storag element
the full control circuit
the empti control circuit
the detect circuit
the data storag element
the common move signal
signal set
predict signal propag time
movement of a data element
control structur for a high speed asynchron pipelin
chain of control circuit
an empti control circuit in the chain
adjac control circuit

a full graphic imag for input
vector gener scan convert
vector gener hardward
the vector gener scan convert
the printer
the laser printer through a raster data input port
the laser printer
the i/o channel
the graphic imag data
the bottleneck
speed for graphic data
microcod memori
increas printer
imag buffer memori
graphic imag
graphic data from the main processor
graphic data from a main processor over an i/o
an output scanner
a vector gener scan convert
a microcod instruct
a laser printer
a full graphic imag from vector paramet

a full precis quotient in a quotient regist
the sequenti iter calcul of larg radix quotient digit
each quotient digit
divisor
dividend
an arithmet circuit
a single pass through the rectangular multipli
a rectangular multipli

a full precis round bit addit
thi low-precis float point addition/subtract techniqu result in a signific enhanc of perform in float point addition/subtract
the time the full precis float point addition/subtract stage
the pre round logic suppli a carri bit
the normal amount for success low precis float point addition/subtract
the normal amount
the full precis adder/subtractor
signific non zero bit
preround
point normal predict
point normal calcul
point adder/subtractor
parallel with a full precis
comput in most circumst
bit in the opposit direct of normal
a low precis

a full search block
the minimum error function
the error function
the block posit
pixel valu from a search area of a previou video frame
pixel valu from a block of pixel in a current video frame
circuit implement of block
a group of posit of the block in the search area
a group of error function

a function of a random code
short term memori equat for neural network
random binari code
parallel bu interconnect
long
local synchron of the processor
inform in the form
exchang of signal
array of parallel processor exhibit behavior of cooper competit neural network
analog inform

a function of the absolut address of the jump instruct
the target address of branche
the softwar develop
the next time the same jump instruct
interdepend of the nth
interdepend control
comparison of the index regist field
an index regist

a function regist
the slot structur
the inform content
respect address regist
function regist
each slot
complet inform
an electron data
a slot structur
a plural of slot

a further extern port
the signal processor of each group
the local 2 port of anoth processor
the control of a group control
serial parallel digit signal processor
processor of a group
local 2 port
intern interconnect among the port
each signal processor
a switcher control
a switcher
a plural of vector processor

a futur file
the futur file

a fuzzi infer engin
unari number
the unari valu
the rule evalu modul
the onli time
the fuzzi logic oper
the fuzzi infer engin
rule evalu modul
more tradit binari number
fuzzi logic oper with a high degree of accuraci in a minim amount of time
fuzzi logic oper
decod an input
a unari valu
a rule evalu modul
a rel strength of a fuzzi infer rule
a fuzzif modul

a gage
the liquid flow
that chamber
probe
liquid flow line
gase in a liquid flow
gase
depress of the liquid level in that chamber
chamber
a regul
a pressur drop
a gas/liquid

a galoi field error evalu
success one of the coeffici of each polynomi in success memori access cycl
success iter of a recurs algorithm
real time success approxim
hard wire serial galoi field decod
each coeffici of the polynomi
correct processor
an error detect
a new version of the coeffici
a galoi field error locat

a gateway
user with current oper statu of the system
user at remot locat
transfer between respect control devic
thi virtual offic
the telephon network
the telephon equip within the offic
the telecommun environ of a small offic with an interfac
the pstn
the person comput
the pc with a plug in card
the devic interfac with a comput
telephon traffic for a single user within an offic over the equip
telephon equip
telephon environ
such standard offic capabl a messag
standard telephon interfac
respons data through the input button
respons data
real time configur adjust
own devic
multipl user
intellig
input button
facsimil machin
differ offic
devic for a small offic
data commun within the offic
configur the system
an isdn interfac
an audio interfac
a virtual offic
a stand alon unit
a scalabl network
a programm control processor
a plural of such devic
a network environ

a gcd
use in the error correct field
thi apparatu i
thi apparatu
the proces
the bch
the algorithm for the signal process in the convent commun line
solomon code
onli refer clock
multi error correct
kind of cell
error in system
correct error in posit
capabl of the code
an lsi becaus the circuit scale
an evalu cell
an error posit
an error evalu
accord with the error
a syndrom cell

the operand regist
a plural of operand regist

a gener
write in data for an operand regist
the input of the arithmet unit
the arithmet unit after the operand for the instruct
renew i
output of the oper stage of the arithmet unit a input
output of oper stage of the arithmet unit
operand for the instruct
operand determin signal
operand determin
either output of the plural of operand regist
an output of the plural of oper stage of the arithmet unit
a stage of the arithmet unit
a regist number
a plural of data buse

a gener interpol pipelin processor for use in a real time video display system
the coordin of ani point
gener interpol pipelin processor

a gener purpos hardwar acceler
the alu input port
programm data path devic
output into the regist of that cell
eprom
data path control word
coupl the content
an address modul
a wide varieti of digit signal process function
a single system
a programm data path devic

a gener purpos microprocessor
the variou function
the termin adapt
subtask
thi second stage
thi preparatori stage
these subtask
the subtask
the presenc of data
stage with an option fourth stage
stage a the basi
relat in the third stage
parallel on a multipl processor databas system
databas relat on a common field in a parallel relat databas field
an assign stage the detail
a preparatori stage
a manner that the processor
part count
reliabl
the program into command in a process form
the process on a command basi
the normal valu
the next command
the execut of the command
the error reoccur in the middle of the command
servic of the inform processor
individu operand of an instruct
function in an inform processor
control apparatu
avail
thi data avail
these potenti conflict
the oper of an instruct pipelin in a comput
the insert of an appropri number
the effect end of the pipelin
the effect begin
the conclus that no actual resourc competit
the avail of data
slow rate
instruct into the same pipelin stage a a third non conflict instruct
end of the pipelin
apparatu function
all potenti resourc conflict
all instruct in the pipelin
apparatus/method for error
a program under pipelin control
a normal valu
a next command
a manag system of the occurr of the error
normal termin adapt
isdn termin adapt
isdn oper
a termin adapt for isdn servic

a gener purpos multipli
the myriad function
gener multipl function
continu process activ
booth
the second portion
the number of gate drain delay within the variou data path through the array
the multipli circuit
the first portion
signific bit of that product
multipli circuit
a multipli circuit
a horizont pipelin latch
binari input number
an output product
adapt lm
a seri of multipl

a gener purpos regist file
virtual manner
the multi precis execut unit
the media processor
the gener purpos
resourc through the network
radio
programm switch
programm media processor
partion multi precis arithmet unit
parallel gener purpos media processor
pair wire
multipl precis parallel oper
multi processor oper
media data stream over the commun fabric i
media data stream
mathemat element
high bandwidth memori control
gener purpos
fiber optic cabl
encrypt
data cache/buff
authent
a memori channel
a media data stream
a high bandwidth extern interfac suppli media data stream

a gener stage
virtual effect address
virtual address capabl
the first translat buffer
subset of the second
effect address gener on an instruct by instruct basi
effect address calcul unit
conjunct with a doubl word of instruct data
branch instruct through an instruct pipelin
an indic of an occurr of a branch instruct
a translat buffer
a second translat buffer
a plural of branch mark bit
a half word basi

a geometr logic unit
version
transform in grayscal imag
the geometr logic unit
the data within rang
select function
represent
clip the result data
an alu control
a word by word basi
step of the data
select bypass of stage in an asynchron microprocessor pipelin
extern logic in synchron with a clock
elast self time interfac for data
data in a plural of step
data from the stage
a transceiv
a plural of consecut stage

a global aggreg result row by a global aggreg oper
the local aggreg oper
the aggreg result row
sql queri in a relat databas manag system
row of the tabl
optim of sql queri
more aggreg result row
global aggreg oper
aggreg express
a local aggreg oper

a global program counter
vector calcul
those pipelin stage
the vector mode
the stage program counter count
the plural program
the global program counter
the concurr execut in ani mode
suppli instruct address
respect first avail pipelin stage until the vector calcul
pipelin mode
pipelin instruct address
pipelin instruct
own stage program counter
other program
instruct from plural program
effect effici control of program execut
ani other pipelin stage
ani number of the pipelin stage
a vector mode
a special case of the pipelin mode

a global regist file
the global regist in that global regist file
the global regist
the entir regist valu
simultan request
global regist for a multiprocessor system support multipl parallel access path for simultan oper on separ set of global regist
global regist for a multiprocessor system
each set of global regist
each global regist file
atom arithmet oper
a single global regist file

a global regist file via an inter pipe bypass
younger instruct
thi multipl execut pipe architectur
the sourc regist operand
the regist operand
the other execut pipe
the number of execut pipe
the multi level schedul system
the local regist buffer
the local instruct schedul
the global instruct schedul
the execut pipe
system exception/trap
sourc operand valu of the instruct
share
second execut pipe
operand valu
number of instruct with the execut unit
multipl local instruct schedul
multipl execut pipe
instruct branch predict techniqu
instruct among the execut pipe
execut pipe
each local instruct schedul
control in a processor architectur
anoth execut pipe
an inter pipe operand request
an inter pipe bypass
a transfer of the sourc
a simple global instruct schedul
a multi level instruct
a local regist buffer

a go to null network
to data network
the threshold logic i
the reset network
the registr network
the output signal line
the go to null network
the go to data network
the direct signal
system initi at registr boundari
state at the output signal line
signal i in the null state
registr network
dynam threshold gate
a threshold gate with registr
a reset network
a number of the data input
a null state at the output signal line

a grace degrad capabl
video frame
video decod engin
video decod
the video decod engin
the remaind of the decompress
the mpeg
the more upper data layer
the host microprocessor
stage pipelin structur
processor and/or the graphic acceler
occasion video frame
mpeg processor
minimum cost
minimum capabl
lower data
decompress the mpeg upper data layer
comput decompress task between the comput system host microprocessor
best use of resourc in the comput system
ani part

py
px
pixel for each span
perspect correct factor
interpol paramet valu for pixel along each span
gradient calcul system
an imag from a plane equat
an edg stepper
a span stepper
a perspect correct factor w
a gradient for each pixel
a gradient calcul system

a graphic display devic
three dimension graphic
the storag content of the error regist
the lumin data
the error data
the boundari error data
the anti alias method function in real time
success pixel
scan line on the screen
lumin data
hidden surfac process devic
error of a plane segment
error inform
devic obtain lumin data
correct for boundari of the pixel
anti alias process
anti alias method
an error regist
an error data
an anti alias method
a three dimension polyhedr object on a two dimension screen in accord
a right boundari

a graphic process system
triangle processor pipelin
three dimension object on a monitor
these polygon
the polygon processor pipelin
the polygon descript
the pixel of that scan line
the first scan line
the descript of the polygon
the crt
that scan line
scan line order
polygon processor pipelin
pass through the polygon pipelin
overflow condit
new polygon
halv of a display screen
frame buffer control
extra area
each new scan line
clip onli polygon
both shell
a uniqu clip algorithm
a pipelin of polygon processor
a guardband space
a group of two dimension polygon

a ground
visual display system of the comput
the surfac detail store
the purpos of the perspect transform
the perspect transform comput
the display plane
imag type
computet in real time the perspect transform
a visual display system of the comput
a visual display
a trapezium scan of a photograph imag
a surfac detail store
a surfac detail inform store
a surfac detail gener
a rectangular raster scan display
a perspect transform comput

a group of data
the function modul
the control element place sourc
multibu processor
destin address on the bu sourc address
destin address line
a single machin instruct cycl
a plural of machin oper
a plural of individu line
a plural of elementari function modul in circuit connect
a pipelin effect
a group of sourc address line
a group of destin address line

a group of dma
the sub control with less frequent access of system main memori
the io control
the dma transfer request
the dma transfer for a plural of io devic
the command data
sub control
specif io devic
request quad
main control
input/output control method
expans of the system
each start request quad
data structur for mani sub control in order
complet statu i
command data
an io control for each group of the io devic
a specif entri in a complet list
a number of block

a group of execut unit for execut
the intermedi storag buffer
single cycl instruct dispatch in a superscalar processor system
placement of result
instruct dispatch in a superscalar processor system
each time an instruct
dispatch multipl instruct
ani requir
ani destin operand
altern gener purpos regist
a plural of intermedi storag buffer

a group of instruct
the power consumpt of the microprocessor on the target instruct in a cach miss state
the power consumpt of the microprocessor on the target instruct in a cach
the power consumpt of a microprocessor with the use of an instruct file
power consumpt of each instruct

a group of line of subscrib
the variou subscrib in accord with frequenc
the telephon exchang
the subscrib
the dsp comput resourc
the chronologi of recept
the calcul of filter stage
telephon signal
telephon exchang
signal of subscrib
hand
group of line of subscrib
function for the purpos
digit signal process devic
commun a plural of subscrib
circuit on card of subscrib
a telephon exchang
a plural of line of subscrib

a group of memori cell
those sub word line
the word line
the sub word line
the sens amplifi circuitri
the plural of sub sens circuit
the memori cell in the row
the group of memori cell
the control mechan
sub sens circuit
sub
memori cell from differ row of the memori
main word line
each sub word line
a plural of sub sens circuit

a group of program address regist
thread of a program in respons
the long latenc event
separ group of regist for multipl thread
mechan switche between the program address regist in respons
instruct thread field
differ thread
a thread switch
a miss in the level 2 cach
a long latenc event

a group of regist depend unit
these cach line
the regist depend cach
the cach line within the regist depend cach
the cach line within the instruct cach
respect instruct
regist depend unit
out of order instruct issue
no forward data depend within the group of regist depend unit
multipl cach line
cach line within the instruct cach
an instruct dispatch unit
an ident number of regist depend unit a instruct
an ident number of cach line
an earli data depend resolut mechan in a high perform data
an earli data depend resolut mechan for a high perform data
all regist depend unit
accord with the present disclosur
a regist depend cach
a next processor cycl

a group of separ compat instruct
the classif of success instruct
simultan issue
plural decod
least part of an instruct
instruct for multipl issue
execut of that instruct
each instruct in depend
demand on ani function unit
classif
backward propag

a group of target instruct
the sequenti instruct within the queue
the sequenti instruct
sequenti instruct within the queue
run time delay
outcom
more sequenti instruct
minim delay if the predict that the condit branch
each condit branch instruct
detect of a condit branch instruct within the queue
delay if the predict that the condit branch
condit branch instruct execut
condit branch execut
an immin execut of the condit branch instruct
a success retriev of the target instruct
a retriev of the target instruct

a half pel interpol circuit
the valu of the candid vector
the second buffer memori
the pelinterpol circuit
the pel data
the motion vector detect apparatu
the minimum valu a a motion vector
the first buffer memori
peldata of an object block for motion vector detect
peldata of a search area
pel data of a search area within a refer frame
motion vector
half pel
detect of a motion vector
anoth buffer memori
absolut valu of differ between the individu pel for a plural of candid vector
a motion vector of a half pel accuraci
a motion vector detect circuit
a motion vector detect
a minimum valu of the output of the motion vector detect circuit
a minimum valu detector

a halt circuit
the stall in the origin control loop
the stall
the other control loop
the exchang of data signal
the control loop of the first asynchron control circuit
the control loop
that asynchron control circuit
propag throughout the entir apparatu
propag from thi point throughout the system
power dissip
plural of asynchron control circuit
onli caus transit in the circuit in respons
maximum perform upon demand
each asynchron control circuit
asynchron data
asynchron control circuit
an asynchron design
all processor activ
all activ
a single request acknowledg control loop
a request acknowledg control loop
a plural of asynchron control circuit

a hard wire uncondit bit
the mask regist
the mask locat
the mask context bit
the bit locat in the mask bit bank
techniqu for a simd processor
mask context of simd processor
instruct parallel
element in special situat
each differ machin oper within the instruct
address a specif locat in a mask regist
a scalar mask bit
a plural of individu machin oper within a single instruct
a mask context bit
a mask bit bank

a hardwar circuit
type gener purpos memori
the templat
the respect portion
the relationship between data
the pre detect portion
so call templat
section on data transmiss path
main process of templat
ident data
determin in the pre detect portion
advanc with respect
a templat
a pre detect portion
a plural of data section of data transmiss path

a hardwar failur
the occurr of the error
storag subsystem recoveri
recoveri from intermitt storag hardwar failur
multi level storag system
hardwar checkpoint at storag system interfac
duplic of subsystem hardwar within unit of the storag system
command restart system oper
all level of the storag system
a point

a hardwar fast clear capabl
the rang of the frame counter
n region
clear oper
clear capabl

a hardwar implement
the system element behavior
the plural of templat
the plural of regist model
the plural of except event
the instruction/data stream
system event
system element behavior
system element
problemat oper of the hardwar implement
particular instruct
partial behavior
oper of the hardwar implement
instruction/data stream
hardwar implement
except of interest
circuit design with respect
caus boundari condit
an oper of regist
an instruction/data stream
a plural of templat
a plural of regist model
a plural of except event
a higher level implement

a hardwar pipelin processor
ultrason imag
the result imag
the gradient oper
the edg of spot
the edg of specular target
specular target
real time with the gradient oper
nois reduct method
minimum valu for smaller spot
medic ultrasound
gradient oper
acoust speckle
a high likelihood

a hardwar pointer
valu in the stack
use with a system
the top valu
the top posit of the stack
the order statist
the notion of a stack oper
the fine grain comput cell of that system
the entir string
the configur of the circuit
the appropri counter
such requir
ser
jun
greater
each compar circuit
control condit
compar stack architectur for order statist filter of digit imageri
compar circuit a posit in the stack
a high perform architectur for imag

a head address of a macroblock
the second address calcul
the first address calcul
the address format
second address calcul
parallel like a pipelin
memori store address
memori access like a real time imag
an overhead of the address format time in the instruct
an exclus hardwar
an address format circuit for an imag
an address format
an address base memori access into a rectangular area
address pattern
address of pixel within the macroblock on the basi of the head address
address format circuit
a sequenc control

the dma control
dma data

a header in the dma buffer
the recipi group
increment mode
graphic subsystem with smart direct memori access oper
each chunk of data
ani data for a group
and/or the regist
an increment mode
all regist in a group
a smart dma control
a hold mode
a high effici dma oper

a heapsort processor
the second decod
the second bit line
the first bit line
the data on the second bit line
the data on the first bit line
the data of these bit line
the data of the parent
the address of the parent
processor circuit
part of a heapsort algorithm
origin macro cell
macro cell pair
larger data in macro cell pair
gener of heap data
data of a macro cell
a parent macro cell
a macro cell

a heurist select process
unit of the microprocessor
thi one
the individu instruct of thi program
the earliest possibl execut cycl
rapid process of a program on super scalar microprocessor
precursor instruct
pipelin conflict
instruct of a comput program into instruct group for parallel process
execut a minimum number of delay cycl
control flow depend
an instruct group
account of data flow depend
a way that the instruct
a minimum number in a list

a hierarch cach architectur
the use of store in type cach at level
the use of cach memori
the store through type
the number of memori bu access
the disadvantag of prior system
the disadvantag
the cluster
processor cluster
hierarch cach memori
each level
each cluster
cach pair within a cluster
cach in thi manner
a plural of level
a level

the slave data cach
a store queue
a slave data cach
a master slave cach system

a high bandwidth of instruct
valid bit for each slave
thi tight coupl
the master slave cach system
store-to instruct stream detect
smaller direct map slave cach
set of address tag
set associ master cach
master slave cach system for instruct
data operand
coher oper
cach manag oper for the slave cach
cach data
an instruct pipelin of a processor
an execut pipelin of the processor
all search oper
a slave instruct cach
a slave cach
a low miss rate

a high degree of asynchron
vector data logic usag conflict detect
use in a scientif data
time the subsequ instruct
thi conflict
program execut result
overwrit a sourc vector element of an earlier instruct
overwrit a result vector element of an earlier instruct
no overlap
logic usag conflict
complet in the proper program order
categori of data logic usag conflict
a write/writ conflict
a write/read conflict
a scientif vector support processor
a result vector element of an earlier instruct befor the result vector
a read/writ conflict
a number of memori cycl until the correct inform

a high densiti sort processor in a semiconductor
the input port input
the data string
multi input compar
key valu storag devic
k continu set of comparison data
input port
input data string
data input from latch regist
data from k
a sort processor of the present invent

a high frequenc
the write of the oper result by the main oper unit
the pre oper unit into the gener purpos regist
oper result of the instruct
an instruct in a plural of stage in a pipelin mode
a small number of circuit compon
a pre oper unit
a main oper unit

a high level virtual comput in a heterogen hardwar
virtual comput
transfer of data among the processor in the system
the languag inject librari
the heterogen hardwar
softwar in the virtual comput
softwar environ
softwar configur of a virtual comput
runtim server
process control
parallel comput element into a configur
multipl coars grain single instruct
environ for heterogen network comput
effici applic
each processor in the virtual comput
daemon
client/serv
a languag inject librari

a high perform cach system
the actual set of option bit
organ
flexibl system design
flexibl cach system design
few part
cach unit for flexibl usag in cach system design
cach system design
cach featur through the set of appropri cach option bit
apparatu support thi user
accord with an altern embodi of the invent

a high perform comput pipelin
content address writebuff
comput pipelin

a high perform microprocessor bu protocol
memori access on cach
burst memori access
burst bu transact
an sram array cach
a primari cach system

a high perform processor
processor throughput
precis state at ani instruct boundari
precis state at ani instruct
a watchpoint

a higher effici
operand address calcul
each stage of the pipelin mechan hold reserv inform
a write of the operand

a higher level activ
the next pass through the pipelin
the address while a process
sever i/o channel process time share a data pipelin processor
multi process address storag
memori a a process in the pipelin proceed from stage
an address from memori
activ level for each process
a storag array
a next pass
a lower prioriti level activ

a higher prioriti event until the event command
uniform
the link
the event vector
stage through a process
multipl precis event
event command in the instruct
effici handl of multipl precis event in a processor
an instruct from the instruct
an event vector
a plural of event
a link address for the highest prioriti event
a highest prioriti event

a highli parallel render pipelin
z sort i
visual imag
transpar
the use of a link list data
the system of thi invent
the storag of mani pixlink for each pixel
the processor effici problem
the pixlink data
the comput intens render algorithm
techniqu with control
subpixel coordin
single state machin control
primit polygon
polygon edg interpol
pixel coverag
hardwar embodi
g
fraction pixel list
each pixlink vector in a pixel stack
data/control
data parallel
anti alias render oper in hardwar
all imag data valu for x

a histor branch instruct address
use in an instruct
thi event
the instruct prefetch
the histor branch instruct address
instruct prefetch in a data
branch destin address
an instruct request address

a histori base prefetch cach
the time queue correl past event with cach
the time queue
the prefetch target buffer
the prefetch cach
the next time
programm amount
past event
n cycl
input from a time queue
histori base prefetch cach
a time queue
a prefetch target buffer

a histori buffer system
type of data
the subsidiari histori buffer
the recoveri
the main histori buffer
the entri in a subsidiari histori buffer
the control data
tag field
subsidiari histori buffer
main histori buffer
instruct of the same data type
histori buffer system
fxtag
each storag entri
a storag entri

a host
virtual channel
transfer data between the host
the sourc unit
the first function unit
the destin unit
the control transfer data between the respect memori locat
more locat
more address
method for direct memori transfer
messag descriptor block
mdb signal
mdb
locat address
inform therebetween

a host bu cycl
thi state throughout the cycl
the state of the host
the owner of the data
the impact
the host bu cycl
the begin of a cycl
that state of the host
that cycl
read cycl
oper becaus the cach
oper after host bu cycl complet
multiprocessor cach
local processor
host bu cycl
host bu bandwidth
delay subsequ host bu cycl
cycl if the cach control
cach system in a multiprocessor system
back cycl
ani cycl
all host bu cycl
access protocol
a subsequ cycl

a hot water storag contain
valv in correspond with the water temperatur
valv for such system
valv for adjust
the water heater
the respect tap locat
storag contain
single pipe line
sanitari system
mechan drive for adjust
locat for select of water temperatur
faucet
each separ tap locat
control of the water quantiti
cold water
a sanitari system
a microprocessor control with a manual temperatur control

a huffman decod
the index number
the huffman decod
the huffman code
provis of either h
mpeg standard
jpeg huffman
huffman decod
each jpeg huffman
data word in the token
an index number into a lookup tabl i
an identifi

a hybrid execut unit
point execut unit
miscellan instruct in a single clock cycl
hybrid execut unit for complex microprocessor
a result sourc in conjunct

a hyperblock loop
the single iter schedul length
the result schedul
the program loop
the minimum initi
the minim initi
the initi interv i
reschedul the instruct
previou loop iter
more control flow exit point
instruct of a program loop
instruct level parallel transform
an iter softwar
an improv over the previou schedul
a single iter schedul length
a single iter schedul
a single control flow entri
a sequenc of instruct within a program loop
a prior iter of the program loop
a previou length of the program loop
a new instruct order for the program loop
a minimum initi

a hypercub configur
the reconfigur pipelin of each node
the reconfigur pipelin
the masnet
the flow of signal from the memori plane
the capabl of the node
the bulk of all calcul
point arithmet processor
multinod reconfigur pipelin comput
mani power algorithm
larg capac node
integ arithmet logic processor
hyperspac
configur the pipelin at each tick of the clock
basic substructur
an internod data router
a reconfigur pipelin of function unit
a multiplan memori by a memori alu switch network
a multinod parallel process comput

a imag
updat rate
these imag layer
the accuraci
object in a scene
motion of the graphic object
imag layer
gsprite from memori
graphic model
display at video rate
differ rate
an affin transform on the gsprite

a interfac pipelin of the address interfac
the system bu command
the processor command
the duplic tag statu inform
system bu command
processor command
no valid system bu command
more processor modul
duplic tag statu inform
duplic tag cach statu inform
address interfac
address in the interfac pipelin
address for modif of an entri of the processor
a system bu oper in accord with a snoop bu protocol

a jeclear signal i
the state recoveri method
the out of order section
state recoveri
in order retir
execut of a branch instruct in an out of order unit
effici util of processor time
decod section
branch mispredict in an out of order microprocessor
all instruct within the out of order section
a method of state recoveri

a job
virtual memori system for vector
stride access
segment fault
min
max regist
gather/scatt instruct
earli page
a virtual memori manag system for a vector
a rang of address

a jump microinstruct
the target of the microcod jump
that macroinstruct
such microinstruct
simple macroinstruct
more complex macroinstruct
microcod subroutin
macrocod
complex macroinstruct
an appropri subroutin in microcod memori
a tabl
a single microinstruct counterpart

a jump predict ram
predict design for skip/jump sequenc of instruct

a junction
waveguid section
waveguid network
the signal processor of the present invent
the junction
the digit waveguid network
synthesi
other instrument
junction
digit waveguid network
digit reverber
convent digit compon
a waveguid

a key featur of thi network
transfer between the data pipe
these tabl
the select pipe
the load of local memori address pointer
the data pipe
such transfer
sever varieti of select
select of a plural of node
other varieti
node select
miscellan signal
local memori element
individu tag
hexagon grid
extens
dynam rout commun
concurr transfer between multipl pair of node
commun between a plural of node
buss
bidirect systol ring network
adjac partit
a varieti of static rout commun
a traffic control
a systol manner
a ring structur network
a local memori element

a larg capac regist file
the same logic regist use differ physic regist
the logic regist number
physic regist number
parallel execut control of loop
logic regist number
a softwar pipelin
a small instruct field
a result of execut of an instruct
a regist configur
a plural of physic regist number
a logic regist

a larg degree
time cach hit
time cach
the target address for the next instruct
the program execut
the major featur
the condit branch bottleneck
the cach line with instruct
specif function unit
no separ address logic i
instruct cach with multipl instruct per cach line
instruct cach architectur with each instruct field in multipl instruct cach line
effici execut of multipl instruct per clock cycl
an import featur of the instruct cach
altern target address in a separ field

a larg monolith array of cell without uncorrect defect
the von neumann bottleneck of uniprocessor architectur
the input bandwidth bottleneck of high resolut display
the chip size limit
system into a single monolith entiti
off chip connect bottleneck of chip base architectur
i/o bottleneck of parallel process architectur
direct replac cell fault toler architectur
direct logic replac of defect cell by spare cell
a varieti of use properti
a monolith network of cell with suffici redund

a larg number n
the penalti for a cach miss
the context of the current instruct
the context of state element
the averag instruct cycl time for a processor with a main memori access time
processor either stay
process in a comput system
new instruct
multipl copi of state element on the processor
fast processor within a clock cycl

a larg number of differ basic oper
unit of the cpu of a larg scale comput
the unit result in a signific reduct in the number of control word
the number of control word in a brom control store
the number of control word
the function of the unit
the execut of a basic oper
the activ element of the unit
set of control field
control field from other sourc
a set of control field
a read onli control store

a larg parallel path for initi oper stage
up
the schedul issue oper
the result of oper until the result
scan chain
pipelin bottleneck
operand for execut
oper for out of order execut
multi-funct oper schedul for out of order execut in a superscalar processor
execut of an oper
act
a schedul entri

a larg portion of the peripher circuitri
the share
the major perform advantag of risc processor
the major hardwar resourc within the integ
integ datapath for a risc processor
float point execut unit
float point datapath for a risc processor
datapath result in a more effici use of the hardwar
datapath
averag power dissip

a larger physic regist
thi occurr
the size of a logic sourc regist
the rat unit
the rat in program order
the physic sourc regist
the partial width stall condit
the logic sourc regist
the last oper
the data for that logic regist
that logic regist
set of oper
physic sourc regist
perform for the microprocessor
partial width stall within regist alia
partial width data depend
overal superscalar
macroarchitectur
the rat array
uop in futur cycl
uop
the intel architectur
the data for these logic sourc
tabl
the practic
the order of the input instruct
super scalar comput architectur
sequenc inform
retir of instruct result
remand
processor control word
out of order execut of instruct
multipl regist
multipl input instruct
integr of sequenti
destin data in the gener purpos regist
branch delet
anti depend problem while integr of sequenti
a super scalar comput architectur
processor devic
power pc
point regist alia
point rat
physic sourc
parallel for all up
parallel for all uop
new physic destin
mani multipl bit physic regist
logic sourc
integ regist
indic into a rat array
fals data depend
an alloc
alpha
advantag of a larger physic regist
a separ integ
a regist alia
a re order buffer
the rat
a size comparison mechan
a partial width stall mechan within a regist alia tabl unit
a partial width stall mechan

a larger set of physic regist
the abov alloc scheme
store buffer
specul instruct
set of resourc
resourc within the microprocessor
particular instruct in an effici manner
instruct retir
instruct from alloc
entri of microprocessor resourc
effici usag of the microprocessor resourc
dynam alloc of multipl buffer in a processor
buffer size
an instruct from alloc pipestag
an instruct from alloc
a load buffer

a laser instrument
usabl output in the form of display
the processor convert
the oper of the laser instrument
the laser instrument along the surfac
sever squar feet
rapid measur
printout
pipelin corros
pipe section
other surfac from sever squar inche
laser light across a scan area
laser light
immedi use
evalu of corros on signific portion
evalu of a larg area
corros
automat
an automat corros measur system
a processor control

a latch control unit
unit into the memori unit
the latch of the operand
the latch of the data
the instruct detect unit
the data at the data
own memori access
oper in a clock
data and/or an instruct
an instruct detect unit
a pipelin processor system

a latch hold function
the single phase global clock
the single phase clock
the metal grid structur
single phase clock distribut with minim clock
scan data
multiplex scan
multipl clock frequenc
local clock buffer
function mode of the multiplex
function data
a single phase clock signal i
a single phase clock in a processor design
a reload of latch data
a metal grid structur
a local clock copi
a local clock complement of the single phase clock

a latenc predict bit
unnecessari recircul
the valu of the lpb
the lpb
the likelihood of that depend
the execut of ldi instruct
that ldi instruct
such hazard
number of machin cycl after that ldi instruct
microarchitectur
ldi instruct
latenc predict

a later instruct
the bypass line
termin of execut of the other pipelin
superscalar processor with direct result bypass between execut unit
result address
execut in the other function unit
compar in execut unit

a lattic filter mechan
vector lattic propag instruct
valu of vector z in a single instruct cycl
valu of a vector

a lengthi pipelin delay
the wait
the issue stage
storag for inform
sourc for an operand
regard for the avail of operand
pipelin hold up
oper in the schedul
oper from an execut pipelin
oper for out of order execut by a set of execut unit
increas execut unit util
fast oper
execut of the oper
complet of an oper
anoth oper
an operand forward stage
all inform
a wait

a level of author of credit
transmiss of payment inform
transact result in a gateway payment architectur
the servic signal
the server commun
the payment instrument
the payment inform
the gateway over a first commun link
support for addit messag type
servic signal
credit
transmiss of data from the merchant comput system
return author
network electron payment
credit collect
compliant i
anoth payment instrument
all servic request
a server
a second commun link
a payment instrument from the merchant comput system

a librari of pre design function block
these pre design function block
the pre design applic specif function block
the need of a specif applic
the function block
the applic specif processor design method
invoc
complex process function
certain paramet
applic specif processor
a specif applic

a line buffer
the line buffer
the float gate memori cell array
the data request
second pipelin circuit
request for the same data
local of access inform
local access time
linear
less total access time
integr circuit configur
conjunct with a microprocessor
an integr circuit memori array configur
a major of the data request

a line of storag
the symmetr natur of the issue posit
the narrow regist
the last instruct in program order
the averag number of instruct
the averag number
symmetr issue posit
suffici storag for instruct result
portion of regist
narrow to wide depend
multipl line of storag
maximum number
locat within the line decreas a the averag number
instruct increas
each regist within the microprocessor
buffer tag
buffer storag line for execut result
anoth advantag of the futur file for microprocessor
a sourc operand for anoth instruct

a linear pipelin
respect block of data
digit signal process circuitri
block of data element
addit in a carri
adder network
a plural of inner product

a list of the instruct for alloc
vacant entri
the system interrog
the reserv station for that cycl
method for entri alloc for a buffer resourc
knowledg
instruct inform
inform from the previou pipestag
each pipestag
dealloc vector from the abov inform
dealloc vector
cycl pipelin
bit of the preliminari dealloc vector
a set of specul stall signal
a preliminari dealloc vector

a list of the regist number
these regist number
the store data
the regist number of destin operand of instruct
the read stage
store data from a regist file
store data befor an earlier store instruct
sourc operand for the instruct
simple anti depend pipelin inter lock control in superscalar processor
execut pipelin for both execut unit
earlier instruct
a sourc of store data
a simple antidepend interlock
a read stage

a load instruct that load global data into local process element memori
thread into a single thread
the instruct on set
result imper process of thread
plural thread of comput in storag
a respons phase
a request phase

a load multipl regist
use in the operand
the total number of regist
the regist in the subset
the output of the exclus or circuit i
the lmr instruct
the event that a next sequenti instruct
regist of a subset of gener regist
phase of the next instruct
perform enhanc for load multipl regist instruct
complet of the last execut cycl of the lmr instruct
an odd number
an exclus or circuit i
an even number
a target regist

a load pipe
vector processor with byte access of memori
the valid data
the same number of entri
the plural byte data
the mark bit stack
the load pipe
the entri of each mark bit stack
mark bit stack
mark bit
input/output of vector data
data of a plural byte width from the main memori
an oper unit in accord with the mark
a plural of entri of an 8-byte width
a load/stor pipelin from a main memori

a load target circuit
load target buffer
a loop and/or stride

a load/stor function unit
the store buffer entri
the output from less signific entri of the buffer
the load/stor function unit
more signific entri of the buffer
high perform load/stor function unit
data cach of a superscalar microprocessor
a store buffer circuit
a plural of store buffer entri
a plural of reserv station entri

a local arbit
thi fact
the state machin implement
the dual access memori
such transfer with no wait state
multidimension path data interfac with a plural of local microprocessor
elimin of wait state in data transfer
each local microprocessor
each dual access memori structur
each dimens
dual access memori
digit motion control architectur
a transfer between a local microprocessor
a programm logic devic state machin approach
a plural of dual access memori structur
a mode of oper

a local regist cach
the mem interfac
the local regist in the regist file
the local regist cach
single cycl coprocessor
separ machin bu access
port of the regist file
mem interfac
load effect address instruct
instruct word per clock
instruct on the reg interfac
independ read
effect address calcul in parallel with instruct execut by the single cycl coprocessor
each call the local regist
depend between the instruct
collis between instruct
and/or the branch
address comput for load
a stack of multipl word local regist set
a return the word
a regist file for differ type of instruct
a regist coprocessor
a multipl cycl coprocessor
a memori coprocessor
a mem interfac

a locat in the cach
the second cach access
avail pipelin sequenc

a locat in the regist
the tabl i
the empir aglorithm
the branch histori tabl store in each entri a number of bit for each branch address
refer memori
occurr of the branch
occurr of a branch
histori
branch predict unit for high perform processor
an empir aglorithm
a predict for thi particular pattern of branch histori

a log convert
respect stage
log signal

a log unit
the system cost
the program of an instruct rom
the adpcm algorithm
small size
other adpcm rate
consider of low power consumpt
ccitt
adpcm algorithm
a mobil commun system

a log/invers log function
the invers log signal
system for an fir filter
sequenc of log signal
log/invers log convers of signal
invers log signal
fir
each log
a sequenc of input signal i
a second order polynomi
a plural of term signal

a logic address for oper with function unit of microprocessor
the x86 architectur
the main instruct
the linear tag array
the content of a microprocessor cach
linear tag array
fast translat
an extern bu
address microprocessor cach
address cach
a physic tag array

a logic address for use with a processor
the logic address portion
the complet logic address
tabl searche by the memori manag unit
statu field
logic address translat for memori manag unit
inform on the processor
each level of the tabl search
an on chip memori manag unit
an analyz unit
an address captur circuit
a tabl address
a tabl access address
a portion of the logic address
a map ram

a logic address gener
the physic address gener
the logic address of a new instruct
the logic address gener
physic address modif
parallel on success instruct
logic address gener
instruct prefetch system
instruct from the instruct buffer
instruct address through the selector
an instruct from the instruct buffer
a physic address gener
a logic address of the operand
a logic address of an instruct

a logic cach
physic cach
hierarch memori system with logic cach
an odd pipe vector
an even pipe vector
address translat unit
a servic
a sequenc of physic address
a plural of input/output processor

a logic circuit simul
the spike analysi
the spike
the schedul of an unknown output event on the gate in question
the pipelin signal
the function of gate output signal schedul in respons
spike analysi in a logic simul
parallel pipelin oper
other devic of the simul
gate propag delay data
gate input stimuli
anoth devic
a spike condit at the output
a spike condit
a plural of autonom devic
a part of the overal simul function

a logic instruct cach
unit for comput
the throughput of data
the rate of a basic clock period for the comput
the instruct in the cach
the instruct execut rate for the comput
the function of the instruct
the execut of the instruct within the central processor
the concurr comput of program count
the combin of the logic instructiion cach
the address field of the instruct
rate of instruct
instruct execut command
field of the instruct
an output buffer

a logic mean
threshold element
the number of assert input
the gate output switche
the gate exhibit hysteresi
the assert state
programm gate array
more complex threshold gate
asynchron logic
assert while the number of assert input
an assert state
a threshold valu
a threshold gate
a set of cell
a programm gate array

a logic network
the processor of the modul
the next modul in cascad
the memori of each modul
the input memori of the first modul
the input memori for the next processor
step orient pipelin data
architectur for step orient pipelin data
an output memori for the processor
an addit memori
a read/writ random access memori
a read out memori
a programm gener purpos processor
a program for the processor
a potenti memori

a logic oper circuit
the logic oper circuit
the instruct signal gener circuit
n bit code
logic oper circuit
bit a an output logic numer
an instruct signal gener circuit
accord with a combin of a first input
a second input logic numer

a logic operand address
the respect cach memori
purg capabl
operand cach memori
logic address memori
instruct while the other store logic operand address
a softwar instruct
a purg unit

a logic regist refer
the repeat instruct
the instruct loop
such case
non instruct base regist
loop hardwar
ie
each time the instruct loop
contrast
use in a sensor system
thi line
these edg
the surrounding
the pipelin principl
the form of a sequenc of point of high contrast
the camera
so call edg
section with a strong direct chang
section of equal curvatur
rough segment apparatu
possibl contigu piec
piec
half tone imag
edg of an object
coars segment
arrang for the segment of line
configur the regist
an instruct loop
all subsequ instruct
a physic regist refer

a logic structur
word boundari
thi logic
the degree of an address
the avail of instruct
number of transistor
issuanc of an instruct from instruct decod
instruct misalign detect
avail flag regist
an avail flag
accord with misalign inform

a look ahead mode of oper
separ stream of instruct
processor with look ahead mode of oper
pre fetch operand
look ahead mode

an execut control unit
the target perform valu
the perform control puls
period in accord with the perform control puls
perform control puls in accord with the target perform valu
an execut period
a target perform valu
a ratio of a puls width
a puls period of the perform control puls
a perform of an inform

a look up memori
the sequenti step
the perform of the system
the occurr of a memori busi condit
pipe line
locat for the data
address prepar
a single arithmet logic unit

a lookahead address
w
variou modif of thi techniqu
the record after an idl period of l clock cycl
the nonsequenti record address
the nonsequenti record
the lookahead record a the output if the nonsequenti address
the lookahead address
the idl period in respons
the idl period
the effect latenc for nonsequenti memori access
the effect latenc
no output record
low effect latenc for nonsequenti access
cach system
cach output record in respons
cach a an output if the nonsequenti address
a record address
a nonsequenti record address
a nonsequenti record
a lookahead record from the lookahead address after the idl period in respons
a lookahead circuit

a loop circuit
the rest of the program
the number of complet of the loop
the end of the loop portion of the entir program
the delay in loop execut
regist in the data processor
refresh the program counter with the address of the first instruct in the loop in respons
pipelin execut of the loop instruct
execut of the instruct in the loop sequenc
execut of a program loop control instruct
execut n time of a sequenc
each end of sequenc signal
data processor with loop circuit
an instruct counter
an end of sequenc signal upon each complet of the loop
a program of instruct
a loop counter
a loop control instruct

a loop counter in the instruct sequenc
the pre determin number of iter
the length of the string
the instruct return
mani iter
ani extra iter
addit iter
a pre determin number of iter

a loop in a sourc program
thi loop
the valu of commun depend vector
the result of the analysi
the manner of commun of operand
the array index space
loop execut
data depend vector
compil for parallel execut of a program
commun vector
commun depend vector
all area of the index
a loop onto a plural of processor

a low frequenc em sourc signal i
the time and/or frequenc shift
the sourc signal
the centerlin of a stationari pipe
roller
pipe wall thick without remov of extern pipe insul
pipe thick detect around obstruct
pipe inspect
metal clad
larger diamet pipe
em
an open ring

a low level
the estim
the end of the next instruct cycl
the displac field
stall condit from the cpu
pseudo
long instruct word architectur
fast memori access
cycl address gener
bit from a displac field in an instruct regist
bit from a base regist through hardwar logic circuitri
apparatu estim the memori address
an instruct cycl
an estim of the effect address
a mathemat comput

a low rate signal process section
window discret fourier transform
wideband radar detector
the signal detect section sweep through a rang
the output signal i
the magnitud of the complex valu
the low rate signal process section control sweep paramet
the high rate signal process section
the fundament energi content at consecut point in the sweep
the complex valu
high rate signal process section
an alert i
a wideband radar detect apparatu
a signal detect section
a set of complex valu
a pair of single cycl sinusoid

a lower delay summat
workload
work alloc
threshold in ani data
the workload
talli of data
load balanc
imbal
each work alloc
data process work load
control unit of a peripher system
assign of peripher devic
a work alloc
a summat of all delay in each control unit
a separ delay
a mean valu of the differ delay summat

a lower limit
the rulebas
the rule evalu process
the process of the fuzzi input valu
the plural of fuzzi input valu
the lower limit valu with respect
the lower limit valu
the largest valu
the fuzzi input valu
more fuzzi output valu
lower limit valu fuzzi input
an insert sort method
a second list
a rulebas
a rule evalu process on a plural of fuzzi input valu
a plural of rule
a plural of fuzzi input with a plural of fuzzi output
a non lower limit valu with respect

a lower panel of the display
virtual memori array
time requir for access
the write of pixel valu
the virtual array of the dram
the panel of the array
the other panel
the next row of pixel until a panel
the dual panel display
the display proceed
structur of display pipelin
pixel locat of the dual panel lcd
panel
locat of the display by a display pipelin
comput system with dual panel lcd display
color liquid crystal display
an upper panel of the display
a row of pixel in a panel

normal oper
the smram
the main memori space
system manag mode
protect
optim speed
execut in system manag mode

a lower pipelin unit
time from the data slave
the stream
the process state
that slot
prioriti over the other stream
paramet between pipelin unit
number of the slot
independ stream of instruct
data processor with paramet file
consist
a slot
a seri of pipelin unit
a number of pipelin stage
a number of paramet file

a lower portion of the target address
the upper portion of the target address
the upper portion
the target finder
the same time the branch instruct
the same 2k byte block that the branch instruct
the lower portion of the target address
the initi predict
the finder on each branch resolut
the finder array
target address in the finder
regist indirect branche
previou 2k byte block
differ block encoding
branch resolut logic
block number of the branch instruct
block number
block base branch predict
address of a 2k block
a target finder array in the instruct cach
a target finder array

a lower shifter
the lower shifter
shift
underflow recognit
the reorgan
potenti guard digit
path nd
no wait cycl
fast multipli add instruct sequenc in a pipelin float point processor
expon build by 9 bit for overflow
digit of the product
digit featur on both side of the data path
data from the multipli m into the align
an underflow the expon result
account of a possibl lead
mmx
input line
data from the lower shifter into the sourc regist
data a a function
an upper shifter/rout
a method of oper

a machin code program
the success of execut
the success of assign
the code block replic
relat
the weight of the synaps cell
the voltag puls
the valu of the coeffici
the synaps cell weight
the synaps cell
the re measur weight
the physic characterist of the synaps cell
the next adjac synaps cell
the new weight of the synaps cell
the current weight
target weight
synaps cell in the direct
synaps cell
new valu for the coeffici
durat of a voltag puls
analog weight in analog cell of a neural network
analog weight in a neural network
an accept limit of the target weight
all synaps cell
accept limit of the target weight
accept limit
a target weight
a synaps cell in the network
a set of coeffici
a new voltag puls
group of memori locat for a success of execut by group
execut of program
data structur definit
data structur alloc
a success of assign of group

a machin languag
the machin languag instruct
the flag memori
the cach memori for the address
state of operand
operand data from a cach memori
flag memori
data into the cach memori
cach memori search result
a result of the search

a machin state
the superscalar type processor
the result of execut in the execut stage
the machin state
parallel process instruct
no branch
delay flag in parallel process
back stage in a state
a valid flag
a superscalar type processor
a plural of instruct from the instruct memori

a machin word
the plural of instruct path
microprocessor with circuit
instruct path in a plural of instruct path
instruct path
an instruct path
an instruct from the plural of instruct
altern pipelin instruct path

a macro block
util effici of oper processor
the block data of the macro block
the assert of the next mb
synchron with the assert of mbsync
next macro block header inform
continu
block data of the macro block
a macro block header

a macromachin
the program memori a the next sequenti instruct address
the micromachin
the macromachin
the macrocod branch instruct
the execut by the micromachin
the branch instruct in parallel
split level control store
partit
thi central memori over a second bu
the same time with destin valid
the overal architectur
sever instruct
output of array data
output array data
operand length bit
interlock instruct execut with the destin transfer of result
instruct format with design for operand length of byte
half word
first in/first out buffer
doubl word
circular partit
architectur with separ code
all result
a set of processor
memori into a macrocod portion
macroaddress
extract from the branch instruct a macroaddress
distinct machin
an instruct sequenc control
a split level control store structur
a micromachin
a microcod portion

a magnet field detector
underground object
the magnet field detector
rel rotat motion
magnet field signal
locat system
interfac with an oper
an upper hous portion
a system for use
a swivel joint coupl the upper hous portion

a main buffer section of a prefetch buffer
the sequenti process of instruct from the main instruct stream
the process of the main instruct stream
the main instruct stream
interrupt of the process of interrupt of the process of the main instruct stream
instruct from a main instruct stream
a method for use in a microprocessor
a main program

a main memori control circuit
vector arithmet unit
vector arithmet processing of vector data
the vector processing
single process mode
simple vector instruct
pair process mode
an address regist group
a plural of set of the abov mention data

a main memori data
window start pointer valid regist
window start point regist
the window start pointer regist
the valu of the window stride
the valu of the window start pointer valid regist
the valu of a window stride
the regist field in an instruct
the pattern of thi convers by a valu
point regist than the number
point regist pre load instruct
point regist number in an instruct
point regist number by the convers circuit from the valu
more regist than the regist

the retir process
the result of instruct execut
the mqueue
the ifetch
order execut of instruct in a processor
memori instruct
instruct from an instruct cach
each arbslot
buffer slot
a trap vector gener
a memori instruct queue

a main memori from the ifetch
the st/ld hazard resolut system
the depend load instruct
store to load hazard resolut system
st/ld instruct depend
st/ld depend among the memori instruct
method for a processor
instruct from the mqueue
hold until the store instruct
hazard resolut system
a st/ld hazard resolut system
a panic trap indic

a main memori level
the number of bu line in the first memori array
the number of bu line
the main memori level
the intermedi memori array
set of buffer array bu line commun
set of buffer array bu line
second intermedi memori level for use between a central process unit
second intermedi memori array
multipl width
more buffer array
more buffer
intermedi memori level while data in the other intermedi memori level
electron comput memori system
commun buffer
bu line
an electron comput memori system
a number of bu line

a main queue
the shadow queue
the same cycl that the micro oper i
the main queue into the next process stage in a first cycl
the main queue
intstruct in a first queue
a split queue system for a decod
a split queue system
a shadow queue
a second queue
a next process stage

a manner that no arbitr
thi invent speed up the execut of instruct in an inform
the storag mechan in a time
the storag mechan
no processor
data storag unit
anoth processor access the storag mechan
a random access storag mechan

the separ databas
the map manag system
the map
the import of the attribut
the attribut in accord with an access right for the databas
the access right
sever kind of map
separ databas
retriev necessari data from the databas
map manag system in geograph inform manag system
map databas for respect attribut
each map
differ kind of map with use of a comput
differ kind of map
an access right
a map processor access the databas through the map
a map manag system in a geograph inform manag system

a mapper
window in an out of order processor
the valu in the window pointer regist
the specul window pointer regist
the specul valu
the locat of the window in the regist file
the instruct the control
a window pointer regist
a specul window pointer regist
a specul valu of the window pointer regist
a regist window

a marker micro instruct
victim from the instruct cach
victim cach
the victim cach entri
the victim cach
the marker instruct
the marker
the avail of a macro instruct
storag of other instruct cach victim
instruct refetch in a processor
an instruct cach line
an entri in the victim cach
address after a branch mispredict
a victim cach

subsequ processor
those sequenc
the storag posit
the number of time
the first processor in the chain
the data stream
the compress system
the bodi of digit data
that number in associ
storag locat signal
sequenc in the order
separ memori
pair of data element
pair into group
non occur sequenc
memori of each pair of data element
frequenc of occurr
element in the order of probabl of occurr of each pair in the data stream
each uniqu pair link the pair
each pair of signal
data compress with pipelin processor
common lower signific figur
a single output locat
a pair of element in the input

a mask buffer
use with an imag gener
use by the respect region
the obscur mask
the obscur manag for storag
the obscur manag
the mask buffer until the entiti
the mask buffer
the insert logic process
the foreground entiti
single object
polygon processor
polygon in the imag
nearer object
larg group of object
insert
imag viewpoint
foreground entiti
comput element in the imag gener
area modul
an obscur mask in the mask buffer
an obscur manag
an object processor
all object in an imag scene
a region processor

a mask valu
vector data in multipl non consecut locat in a data processor
vector data in multipl locat within the processor
the multi entri input data
a pointer valu
a plural of locat within the input data
a multi entri input data

a mass segment memori
thi data in a segment memori
the uniqu group of label
the subject invent
the segment of a video frame a the segment
the segment label
the segment intens
the segment extractor
the perimet of the segment
the output of the segment label
the mass segment memori
the group of label
sorter
random access memori for featur extract
onli pixel
label for all pixel in time sequenc for a frame of data
individu segment data
individu segment
each segment
classif a target
automat target detect
ani unnecessari data
an algorithm processor
all pixel
adjac label filter
a uniqu group of label
a segment labeler/extractor output segment of video data
a segment label filter
a segment extractor upon request
a segment design
a segment boundari design

a master cach
the other request
sublin valid bit
sub line valid bit with all cach
request in the master
full cach line
each request
a request pipelin in the master cach
a miss from a slave cach

a master interfac
writeback cancel
transact execut circuitri
the writeback request if the dtag index
the transact execut circuitri pipelin memori access request from the data processor
the system control
the invalid circuitri activ writeback request
the interconnect
the dtag index
system for use in a packet
multipl block of data
memori transact request
invalid circuitri
interconnect the main memori
each writeback request
each memori transact
cach tag for each data
cach coher multiprocessor system
an interconnect modul
accord with interconnect control signal
a transact
a set of master cach tag
a respect cach memori

a match between the store oper target address
the store pipe
the self modify code fault
the second address tag
the instruct buffer entri
the first address tag
self modify code fault
second comparison logic i
second address tag
result of a store oper
pipelin stage of the processor
op entri for op
memori address for the instruct
memori address for instruct
instruct buffer entri
first comparison logic i
first address tag
embodi of a seif modify code
a store target address buffer
a store pipe
a store oper target address indic on commit of a store oper result
a self modify code fault
a self modify code

a match flag
the slow arithmet oper
the regist file and/or individu field in the instruct
special purpos regist
program execut control
complex logic oper within a single clock cycl
complex logic oper in a single clock cycl
bit manipul on data
a microprocessor architectur

a matrix multipl method
the calcul in order
product matrix block
matrix multipl for comput with hierarch memori
individu block
high level storag
hierarch memori
elimiant processor
commun of intermedi result
b term matric
a sum of a seri of outer product

a matrix multipl of a column of the second matrix
the set of number between the regist in a time progress manner
the pe unit
the pe column
the partial process result
the number of pe column
the number of column of the second matrix
the multipl circuit
plural of processor element
each pe column
compact
column of a second matrix
circuit configur
anoth pe unit of the pe column
a plural set of number of a row of a first matrix
a plural of bit of the set of number
a partial process result
a multipl of the set of number
a multipl of the first matrix

a maximum number of regist valu
the regist of the regist file
regist per cycl
port bandwidth
instruct of a program per cycl
certain one of the regist in the regist file a sourc operand
certain one of the regist in the regist file a destin regist
access port
a regist file of regist

a maximum of n
the perform of instruct
the execut time for instruct
result of instruct execut between pipelin
a superscalar parallel processor

a maximum ultrasound echo strength
the outer fetal head boundari
the inner fetal head boundari
the initi fetal head boundari
real time interact imag
pipelin fashion
outlier point
outer fetal head boundari
object boundari from ultrasound imag sample
fetal skull thick
fetal head size from ultrasound imag
fetal head size
each radial maxima point
common vertex point within the fetal head imag
an ultrasound system
an ultrasound sample
an ultrasound imag of the fetal head
an inner fetal head boundari
an initi fetal head boundari
a radial maxima point
a plural of radii

the cpu core
the command list code
parallel with execut of the gp instruct
data in accord with command list code
data in accord with a gp instruct

a mechan for dtmf detect
dtmf detect

a member
the output of the processor stage
the m row
processor stage
paramet data
parallel process of local imag data
n imag data
m row x n column of imag data
imag data from a local imag data sourc
an output section
an ic form

a memori access control
transmiss of an invalid inform
throughput of main storag access
the third storag
the tag control circuit
the necess oper circuit
the first storag
the access select circuit
tag control circuit
request at a time
onli store access request
invalid of the tag inform
an access request
a third circuit storag
a tag inform store
a tag control circuit
a store access request
a plural of invalid
a plural of access request of the invalid oper
a new read access request befor an access request
a new access request
a necess oper circuit

a memori access error condit
virtual address tabl look
the virtual address data
the memori pipelin after the instruct
the error condit
the central process unit address data in the memori
recoveri method
recoveri circuitri
memori control circuitri
instruct statu data
each memori access instruct
an error condit
a virtual address memori tabl lookasid buffer

a memori between multipl processor
the plural of the section at a time
the plural of subsect at a time
the plural of subsect
the plural of section
the plural of port of each processor
the memori refer from each processor
the memori path for each processor
subsect conflict between the memori refer
section conflict between the memori refer
memori refer access a particular bank
each subsect
each processor by a memori path
bank conflict between particular memori refer
a plural of subsect
a plural of section
a plural of port of each processor
a method of memori access

a memori bu i
the pipelin circuit
the paramet bu i
paramet of the packet
header
a pipelin circuit
a pictur memori
a paramet bu

a memori circuit in circuit commun
the path of the data
line from a peripher devic
circuit in circuit commun with the peripher circuit
circuit commun with the processor
an interrupt/data
a peripher devic in circuit commun with the memori circuit

a memori control circuit
the memori control circuitri
the memori control circuit
the locat in memori
the error correct code for that data word
request for the data word in question
pipelin error correct
pariti bit
non redund inform
error correct code gener
data word befor storag

a memori display interfac
variabl pixel frequenc
variabl pixel depth
the vsclk control pixel data
the vram frame buffer over the video
the pixel depth mode
the pixel clock synchron
the pipelin clock synchron pixel data
the number of pixel
the mdi
the input control signal feed the pixel data from a vram frame buffer into the pixel
the frequenc of the pixel clock
the dac
pixel rate
pixel depth in a memori display interfac
parallel through the pixel
display devic
a shift clock
a pixel clock from a dac
a pipelin clock

a memori execut pipelin
use of a dispatch pipelin
the memori execut pipelin
the execut of the load oper
the dispatch pipelin dispatch the load oper for execut by the processor
oper with a processor in a comput system
execut of the load oper

a memori hazard
the time between the oper
the separ of the oper
the memori request
the memori hazard sequenc
the memori hazard
separ mark
period end
other memori oper
multipl memori port
memori hazard in processor
memori hazard from the oper
instruct for processor

a memori interfac control
use in a digit system
pixel address collis
memori interfac control
construct of imag with transpar object

a memori locat within the memori devic
use with digit processor
the wait state
the same memori bank of the memori devic
the precharg cycl
random access memori devic
phase of a clock cycl
conflict between the access cycl
an access cycl of a read oper
access cycl
a wait state
a read access cycl
a precharg

a memori manag scheme
word by util of a page regist
the user network
the scan
the programm control
the outsid world a uniform word size
the direct address
programm control
other programm control
job at ani particular time
input/output task
hardwar solut of a user control program in a network node format
differ data base
a particular physic area of the control memori

a memori probe
thi locat
the memori probe
the highest memori locat
regist in memori upon the occurr of a procedur call
microinstruct cycl
each machin cycl
digit processor with bit mask
an output in the form

a memori processor
the same data a the load instruct
the memori processor store
the memori processor intercept all load
the memori pipelin
the loss of effici
the latenc time
the execut sequenc
the compil advanc long latenc load instruct in the instruct sequenc
refer the same address
memori processor
instruct for a period of time
ani subsequ store instruct
a store instruct refer the load instruct address

a memori refer control circuit
the throughput of the total process
the read out instruct in parallel with the extern memori refer instruct
the read out instruct
the operand until the extern memori cycl
the memori refer control circuit
the extern memori refer instruct
the digit processor
intern instruct
extern memori access
case the sequenc
an operand of the extern memori refer
an extern memori refer instruct

a memori subsystem of a out of order processor
unknown address
the architectur state of the machin with invalid data
store buffer in the memori subsystem
respect load
out of order processor with a memori subsystem
mi specul load
load in a comput system
ani store
an unknown store address identif
an unknown address
a store

a memori switch
use of hardwar
the use of a snapshot
the tsw/psw pair proceed through the control pipelin
the task fifo
the same manner
the psw
the next process statu word
the control pipelin
semaphor
preced constraint penalti
passag of data between processor
parent task statu word
operand from a memori unit
method for concurr process of task
interprocess data transfer
execut of that particular instruct
each psw pointer
each activ task
concurr task
all process statu word of the snapshot
a new snapshot
a multipl instruct

a memori transfer
voic recognit
the present invent memori
set of memori locat
sequenti sourc
process inform in the same time frame
pattern recognit applic
particular advantag use within a comput system
parallel with the oper of arithmet pipelin that process pattern recognit procedur
no addit process time
memori transfer unit
memori transfer oper
extern memori control
doubl
appropri data request
a system with an automat sequenc
a pattern recognit system

a memori unit via a common bu
the termin of the memori access
the address pipelin mode
the address control unit
devic for the suspens
devic for a pipelin inform
devic access the memori unit
an address pipelin mode
an address control unit
a request for the suspens

a merchant control comput commun with a test gateway comput over a commun
transact respons
the transact respons
the test gateway comput on the commun
the test gateway comput
the oper of a remot transact clearanc system
the merchant oper comput
the merchant control comput
test transact
a product gateway comput

a mesh like pattern
wire
vlsi
the sourc point
the mesh point
the mesh memori
the lead
search
point array
mesh point on the basi of cost
mesh point
inform of mesh point
duplic inform
cost for mesh point
circuit on the basi of inform
an expans point
a wavefront memori
a sourc point from the mesh point
a mesh memori
system of reconfigur pipelin
reconfigur window select
reconfigur neighborhood function ram
reconfigur delay ram
neighborhood function morphic imag processor
more reconfigur process element group
implement without loss of the reconfigur
imag transform
gener neighborhood window function morphic imag transform
flexibl of the morphic imag processor
an input imag pixel stream
a system of reconfigur pipelin

a messag control block in the main storag of the cpc
the central processor of the cpc
the central processor of that cpc
messag between the processor
each messag from a cpc
cpc
central process complex
an indic bit
an asynchron oper
a synchron oper
a respons
a messag respons block of the main storag
a messag respons block of the cpc

a messag packet
the rout
the node that the messag packet
the messag packet
the destin node from a memori
the begin of the messag packet a part
system with each comput
separ routinng automata for each dimens of the network
rel address indic for each node
portion of the header from the messag
passag
other node a a sequenc of direct
messag packet between the node
messag packet
inter comput messag
each intermedi node
each destin
direct in the header
destin node design
concurr comput system
commun path
circuit of the next adjac node on the rout
circuit at each node
anoth node
a multicomput

a messag receiv in a second node
thi threshold valu
thi threshold
thi signal i
thi protocol
the receiv
the pipelin between the transmitt
the messag transmitt
the messag receiv
the last portion of a messag
the buffer with the messag data
the amount of avail space in the buffer
the amount of avail space
suffici space in the buffer
spatial contigu
packet switch protocol
multipl messag
messag transmiss
messag in the buffer
data through a data transmiss link
a packet switch protocol for a multinod data commun network
a messag transmitt of a first node in the network

a method for depth complex reduct
the imag region
system for depth complex reduct in a graphic
primit for an imag region
object section in a stream of geometr primit
each pixel in the imag region
checkpoint between depth
addit primit for the imag region

a method for memori decomposit in a graphic
the capac of the fragment buffer
system with a pixel fragment memori
system for memori decomposit in a graphic
smaller region
smaller imag region
memori usag of the fragment memori
a portion of the imag
a pixel memori

a method for the automat verif
wide rang of instruct sequenc
uniqu block of memori
thi initi prepar step
these routin
these resourc
the verif of the architectur aspect
the unknown bit
the refer model of the processor
the processor branche
the next block
the instruct rang
the first step in the method
the chanc of detect of a latenc violat
the assumpt
the actual time
the actual result of the test
super scalar microprocessor
result of the test
recomput
modern processor architectur
memori address for pointer
locat by the design simul control
latenc violat
automat verif
an incorrect valu
a specif address
a prepar step
a plural of memori block

a micro control unit
the valu of the chang
the rlog queue read pointer until the rlog queue
the rlog queue read pointer
the rlog base queue
the pointer read from the rlog base queue
the first rlog queue entri
the chang
reset the rlog queue
process in respons
pre process operand
log queue of regist content chang
instruct context for the rlog queue entri
entri in the rlog queue
each time an operand
check whether the rlog queue
base queue of regist log queue pointer for respect instruct
an rlog queue
a separ rlog base queue
a regist chang from the rlog queue
a regist chang for that next instruct

a micro oper
thi result in the effect address
the single cycl execut unit
the memori system execut unit
the calcul of an effect address in a single cycl pipelin execut unit
that result in a single clock cycl
scale factor
displac valu
displac

a microaddress
the storag circuitri
the memori circuitri
storag circuitri
single microrom
processor with single clock
memori circuitri
circuitri in respons
a single clock instruct befor the memori circuit output the microinstruct
a single clock instruct
a microinstruct in respons

a microbranch condit
use of previou dynam microbranch state
the use of the condit
the updat of the dynam condit
the gener of microbranch condit
the earliest possibl time
programm hold on condit
number of microinstruct
multipl cycl microbranch latenc
more cycl
microcod control
flexibl of the microcod algorithm
dynam microbranch condit
dynam microbranch
delay minim
condit branch in microcod execut data path condit

a microcod engin
unit of a comput system
the use of a novel extern pin
the stop of the clock
the middle of a bu cycl
the current instruct on an instruct boundari
the assert of the extern pin
priorit the occurr of the extern signal among other system
phase lock loop
a signal that mask the clock
a sequenc of step
a sequenc of event

a microcod execut unit
valu of the program counter
thi control inform
the sourc queue store sourc pointer
the sourc queue
the sourc operand for the instruct
the program counter queue
the opcod for the instruct
the instruct unit from each other complex
the fork queue
the destin for the instruct
the content of a set of gener purpos regist in the execut unit
the case of operand
immedi data from the instruct stream
either memori
control path between an instruct unit
an uneven process rate
an entri of control inform for each instruct
a sourc operand pointer queue between the execut unit
a sourc operand list
a set of queue in the data
a program counter queue

a microcod rom
transfer gate
the system oper
the rotari stack
the paramet stack
the output of the rotari stack
the next sequenti instruct address
the microcod rom
the data on the i/o
the data in the rotari stack
sequenti clock cycl
regist rotari stack
output microcod instruct
interpret processor
interpret data processor
input buse
increment thi instruct address
an intern rom/ram
an input/output
address of microcod instruct
a paramet stack

a microprocessor in parallel with non float point instruct
the previou microinstruct
the plural of except handler microinstruct
the jump
the detect of the fault
point microinstruct
parallel with non float point instruct
parallel execut of microinstruct
float point microinstruct
a plural of except handler microinstruct

a microprocessor stall
the same regist portion
the same regist
the result of multipl instruct
the result into the real regist file within a single clock cycl
that target differ portion of the same regist
target the same regist
storag into the regist file at the same instant
result of multipl instruct
prior art microprocessor
method for use in a superscalar microprocessor
merg
ineffici stall
implicit flag updat
data priorit
capabl for a superscalar
a special decod scheme
a regist file within a single clock cycl

a microprocessor with on cach memori
y section of the tag field a target data
the tag field of the cach memori
the tag field
second flip flop circuit
microprocessor with on chip cach memori with lower power consumpt
an address translat buffer

a microprogram control
time of transfer
thi program
the whole of the plural of differ program
the program from the program
the plural of differ program
the microprogram control
the address from the program
the address from the microprogram control
program start address
multipl mode microprogram control
microprogram memori
an execut start address
an altern way an address from the microprogram control
an address from the program
a plural of differ program from the program

a milli mode processor
zero in order for access regist translat
the program access regist
the millicod access regist
the alet
the affin between the program access regist number
the access regist number of the program access regist
program access regist number with millicod operand access
an access list entri
alet
a program access regist
a millicod access regist

a millicod
the type of potenti damag
the system state a a result of the occurr
the start of the sequenc
the start of a millicod sequenc
the occurr of a hardwar
the millicod sequenc
the millicod routin test
some stage of the millicod sequenc
retri trap in the processor system
more point in the sequenc
millicod reset
latch state

a millicod gener regist
zero if the word
the valid of a program statu word with a mask
other bit in the word
millicod instruct for test psw valid
load with access test
charact translat assist
bit in the word
bit in the program statu word
bit in the mask
addit the statu

load with access
control in the current millicod
access except for storag operand

a millicod instruct translat
use in execut of the translat
thi translat
the valid of the psw
the program in a gener regist
the interpret of the certain field
the first non zero tabl byte
tabl byte
simple millicod instruct
routin use a tabl of 256 byte
reason perform on translat
an rx format
a string of byte
a special program statu word
a special millicod instruct

a minimum of inter step paramet transfer
reed solomon error
process into a sequenc
on line error detect
correct of error in an optic disk storag system

a minimum overflow state
the intermedi result signal i in a maximum overflow state
the data signal i in a minimum overflow state
minimum overflow state

a mismatch
the target instruct stream comparison a perform gain
the target instruct stream
the target address comparison
the instruct from cach
target stream
target address with an actual target address
mismatch
instruct from cach
data coher in a branch histori instruct cach
a stream of target instruct

the branch histori
branch histori

a mispredict
the specul histori
the specul branch histori
the specul bit
the actual histori
the actual branch histori
specul histori for a branch
recent branch predict for the branch
occurr of the branch instruct
inaccur branch histori
branch instruct outcom
both specul histori
ani recent predict
actual histori for each branch instruct in a branch target buffer
a specul bit

a mix
the next issue cycl
the next clock cycl
the issue cycl
storag in physic memori order
physic memori order
non issu instruct from issue order
non issu instruct
method coordin
issue order
issue of instruct
issuanc
instruct into issue order
instruct into an issue order
instruct in physic memori order
an unrot devic
an instruct latch
activ instruct in a parallel data processor
a pc relat issue order
a new set of instruct
a mixer

a mode
particular control
parallel with simple control
execut of plural instruct
an except process by the same process

a mode flag regist
the vector pipelin set
the vector instruct control unit
the vector data memori on demand
the respect vector pipelin set
system of the present invent
state of the vector instruct control unit
differ mode
control of an instruct control
an oper mode flag
an individu mode with refer
a vector data memori through a pipelin crossbar switch
a plural of vector pipelin set
a plural of vector instruct control unit

a mode select
thi configur
the flash memori devic
the content of other block
the content of a portion of the flash memori
storag of a recoveri bio
recoveri oper
part from the comput system
flash memori area
erasable/programm non symmetr block of memori
dynam non volatil memori updat in a comput system
block of memori
avail updat
ani comput system hardwar compon
a recoveri bio
a portion of code/data
a normal system bio
a normal bio
a non volatil memori devic

a modem for a spread spectrum commun system despread multipath
the output of the processor engin cascad through a pipelin processor
the multipl signal
the demodul processor
soft decis data
each multipath
dual maxima
demodul processor
cell site demodul architectur for a spread spectrum multipl access commun system
a time slice basi
a single seri of soft decis result

a modif
the rel posit
the purpos
the glonass signal of differ frequenc
the accuraci of carrier phase measur
surfac acoust wave
rel posit receiv
rel posit
l2 frequenc of signal
gp carrier phase
glonass signal
glonass satellit
glonass carrier phase measur
differ frequenc of the signal from individu glonass satellit
differ delay
carrier phase measur
carrier phase inform from receiv
both gp
an intermedi frequenc receiv section in order

a modif of the normal load/stor risc oper
vector round integ
vector round
vector revers
point oper unit
memori access in respons

a modul header
the whole block of modul header
the modul program of interest
the modul instruct of the modul program
the modul header of the modul program
the modul header
the modul data
the instuct cach
success modul instruct
section via the operand cach
section via the instruct cach
modul program
modul instruct
modul data
instruct control control other circuitri of the cpu
dual cach memori devic with cach
a modul program

a monitor process second level except condit
the second level except condit
the processor process instruct in order through a plural of serial stage
the process of first level except condit by the except
the point of the occurr of a second level except condit
the point of a first level except condit
the instruct in tandem
second level except
process first level except condit
first level except condit
except latenc

a more accur digit represent of the analog input voltag
vref a an input
use of an interstag gain
these voltag coeffici
the raw digit data from the adc
the error of a plural of most signific bit stage
the effect on error of the digit output word
the digit output word
the digit manipul of thi invent
the accuraci of the result digit output word
second order error
raw adc data
more accur digit represent of the analog input signal be
import for stage of less signific
full scale error
embodi of thi invent
either hardwar
digit correct
capacitor valu voltag coeffici of the msb stage of the adc after calibr of lesser signific bit stage
analog to digit convert with curvefit digit correct
accord with anoth embodi of thi invent

a more rapid algorithm simul
pipelin processor for logic simul

a multi exponenti gain of magnet
veloc
the multi exponenti gain of magnet
the mass flow rate in the individu compon
the magnet
the linear movement of the flow
the individu mass flow rate of a multi compon flow
the flow at sever posit
more arrang of magnet
individu compon of the multi compon flow
fluid flow
flow veloc
flow sensor
differ product of longitudin relax time
differ posit
determin of the equilibrium magnet of each compon thermal equilibrium
a static magnet field

a multi layer switch search engin architectur
the search engin
the packet header
portion of the packet header
more input port
engin architectur for a high perform multi layer switch element
databas memori
a switch fabric
a search engin
a search
a packet header
a packet class

a multi microprocessor comput
the fiber size distribut
the fiber
the diagnosi of neuromuscular diseas
the architectur of the multi microprocessor comput
quantit muscle biopsi analysi system
muscle biopsi tissue
imag of the microscop fiber
fiber size histogram
degree of complex
a seri of individu microprocessor

a multi pipelin microprocessor
the regist field of the instruct
no impermiss depend
an array of compar
all regist field
all combin of regist depend between a pair of sequenti program instruct
addit logic i

a multi predict branch predict mechan
the instruct fetch phase of the pipelin
phase of the pipelin
multi predict branch predict mechan
independ mechan from the other
each condit branch
differ branch predict mechan
a set of rule

a multi processor data
the edg interfac
multipl interfac circuit
each transfer inform

a multi processor p6 comput system that pipelin instruct
transact cycl
the pci configur
the configur transact
the configur cycl
that memori and/or i/o cycl
place if a pci devic
memori and/or i/o
i/o cycl
corrupt in a multipl processor comput system
a peripher devic configur cycl
a pci devic configur cycl

a multi processor system
the re arbitr process
the other processor in order
the first processor abort that transact
the arbitr re synchron process
error correct in a multi processor system
atom
an erron transact
an arbitr re synchron process
an arbitr process

a multi stage pipelin
the probabl of the branch instruct
the data processor of thi invent
non taken branche
mani branch instruct
disturb in pipelin
disabl except
data processor with pipelin

a multi stage pipelin structur
trace memori content
time seri data
the time seri data
the statu flip flop
the output of the statu flip flop in synchron with the output
the input/output termin of the microprocessor
the bu cycl of the microprocessor
the bu cycl
an address for the bu cycl period

a multi stage router interconnect network
the router port
the router i/o element array
the i/o system
pe commun
other address
input/output system for parallel process array
i/o commun
an array of processor element
address i/o ram buffer memori
a router i/o element array

a multi stage techniqu
the differ stage
the confin
subsequ process in success stage
pipelin the interpol process
output of the previou stage
output data in that dimens
multipl data valu
multi stage interpol processor
each stage process
a techniqu for n dimension imag data interpol

a multidimension array
vector signal set
the matrix column
temporari local storag
t plane of p row
t array
systol array for multidimension matrix comput
smaller matrix signal subset
separ column
row signal subset of the vector
row signal subset of the matrix
q matrix
q
p row
matrix vector multipl of matrix
local storag of matrix signal subset
first column
element of the first row
element in the first row
each signal subset
each column
a two dimension array
a three dimension processor
a multidimension systol array processor

a multifunct data
unit in accord with the intern code
the memori from the regist
the intern code
plural data onto the regist from the memori
plural data onto regist from a memori
plural data into the memori from the regist
instruct into a plural of control code
instruct execut of the instruct
instruct at high effici
fashion with each other in accord with the principl
execut of the instruct by the instruct
an instruct execut control unit
an extern memori through a data
accord with respect intern code

a multilevel memori
vlsi techniqu
stack for the function unit
multipl ident processor
master slave mode
geometr data for present on a display
geometr
bit slice circuit
bit slice
a plural of ident processor unit

variou type of data
macroblock

a multimedia data
variabl size block
the variabl size data
the textur buffer
the size of the data
the frame portion
the data from the frame buffer in accord with the mpeg compress algorithm
system for multimedia applic
suppli
z depth
valu of the pixel a an output
the normal vector
stream of pixel
some memori sourc
materi characterist of the object
an input section
a single pixel
a seri of circuit
frame of imag
command from a cpu
an mpeg encod
an mpeg decod
a video monitor
a textur buffer a variabl size data

a multipl access digit commun system
variabl messag length
variabl length messag
the same network a combin
the number of the messag on the network
the network messag
the network interfac unit in turn
the network interfac unit
the messag length
the commun link
the apparatu of the system
such paramet a messag number
such paramet a destin address
permit
one way buse
o
messag segment
messag number
messag group
low duti cycl subscrib
long messag
digit commun system
coupl each subscrib devic
content assign of messag number
all network interfac unit
accord with the invent oper
accord with multipl mode
a signal commun link
a plural of subscrib devic
a plural of network messag
a plural of network interfac unit respect one
a pacer unit

a multipl of regist
ultrason system
third stage
these complex data sample
the tap on the fir filter
the regist pipelin
the q pipelin
the other stage
the number of tap
the number of regist
the fir filter
store success echo data sample
real sample
quadratur
pipelin and/or an imaginari data
output for each stage
fir filter
each regist pipelin
each regist in the pipelin
each filter circuit stage
each beamform channel
decim in ultrasound beamform
data sample
complex input
complex filter coeffici
complex bandpass
array sector
an in phase fir filter
a three stage complex fir filter
a single pipelin
a separ beamform channel for each respect element in an ultrason transduc array
a respect tap
a regist pipelin
a real data
a quadratur fir filter

a multipl part
transform output
the plural of multiplier/accumul
the n intermedi output from the multipl part
the multipl part
the addit part
n pipelin regist
n intermedi output of a multipli
an addit part
addit output from the adder
a wallac tree transform unit
a plural of multiplier/accumul

a multipl pass
un shadow portion of an imag
these depth valu in the raster buffer
the shadow map
the light sourc for pixel
subsequ render
smoother transit
self shadow artifact
nearest geometr primit
higher order
depth valu for each element in the shadow map
depth valu
depth buffer approach
data from the shadow depth map
combin with a global bia
artifact in the termin region
a shadow depth map in a raster buffer
a scene from the perspect of a light sourc

a multipl processor system
the order of the modul
process with pre arrang modul for a multiprocessor system
process pair
place befor activ in the portion of lower modul
order of the modul
multipl independ thread
lower modul
interdepend between the modul
higher modul
each process pair
activ in the portion of higher modul
a portion of lower modul
a portion of higher modul

a multipl unit adapt
the virtual address space of the host processor
the tight coupl
the same memori space a the host processor
task assign control of the host processor
scientif processor port of the high perform storag unit
scientif process system
processor port of a high perform storag unit
more high perform storag unit
high perform characterist
gener purpos host processor
each scientif processor
a scientif processor
a plural of gener purpos host processor
a parallel oper scalar processor modul

a multipl way cach memori subsystem
the way predict
the way of the next microprocessor oper
the last processor code read
the last processor code
the cach memori subsystem
the appropri way
the address bit
slower cach memori
predriven
the way of previou memori read
microprocessor cach memori way predict
hit
the way of a previou memori read
a way select
a single bank multipl way cach

a multipli add block
the signific
the same sample valu
the constant
sum of product function
portion of the constant
plural of multibit constant
level of accuraci
less signific bit
constant
a sum of sequenti output of the multipli add block
a sum of product function
a portion of each constant i
a plural of multipli
a plural of multibit

a multipli array in a processor
the success stage
the stage after a stage
the arriv of the data
self time multipli array
each success stage within the pipelin
data into the pipelin
a standbi state
a precharg state

a multipli cell
transfer digit for output
the row
the respect row
the highest signific transfer digit output
the higher signific column
the first column
success input data word by a co effici word
respect accumul cell
redund radix 2 form
redund radix 2
recurs comput
radix 2
output result digit
order of multipli digit signific
order of digit signific
oper of the multipli
multipli cell
higher signific output
each result digit
each accumul cell
digit signific in the case of transfer digit
digit of higher signific
column in the direct
an input data digit for all multipli cell of a respect row
an individu co effici digit
an accumul cell
accumul cell
accord with result digit signific
a respect input data digit

a multiplicand block
the multiplicand block
the entir multipli block
signific bit of the multipli block
signific bit of a multipli block
multiplicand block
multipl parallel multipl
data a multiplicand block
both zero
an earli out zero skip featur
all zero
a single multipli
a single instruct multipl data earli out zero skip multipli

a multiply/accumul chip architectur
the fraction result
the comput of vector type inner product oper
the architectur of the present invent
post normal result from the addit portion of the system
point number in sign magnitud form
point multiply/accumul oper
oper with a short pipelin latenc
megahertz system clock rate
leading one
inter chip delay
complement form for accumul with the result of a previou product
an array multipli
a product of the fraction portion

a multiprocessor arrang
the transfer of block of data over the interconnect bu system
the program function context
the individu program function of a program process
the execut of a program function by anoth processor
local memori of the individu processor
input/output modul
differ program function
a work queue

a multiprocessor pipelin
high level instruct by a plural
high level instruct
dynam load

a multiscalar processor system
the output of each instruct
separ branch
point processor unit each time
point processor unit an identif
oper without substanti perform degrad
oper in a multiscalar processor system
multipl independ function unit
dummi instruct
a varieti of except

a multistag interconnect network
switch node
output port of the network
multistag interconnect network
multicast commun between processor modul
massiv parallel process

a multistag variabl return address gener
that program without error
termin control
suppress
interrupt sequenc detector
interrupt processor
an instruct classif system with a logic class decod
an activ instruct complet
a subsequ return

a mutex
thread at a time
the thread
the sequenc of step
the process control structur
the process control data structur
the possibl of simultan memori access attempt by the multipl processor
the normal step
the first step of the sequenc
the entir sequenc of step
subsequ normal step in the sequenc in the same order a the thread
specif process control structur
process execut control system for multiprocessor
process execut control system
parallel step on a respect datum
parallel step
multipl thread
multipl data item
method for multiprocessor applic
mani softwar process so that cach local
extens state
each thread
each small piec of work
datum
all step of a process
a softwar procedur
a process control structur
a process control data structur
a plural of thread
a mutex control data structur

a nan operand
the normal flow through arithmet unit
the normal flow
subsequ instruct in the instruct stream
special case
result of oper
pipelin bypass
out of order gener
other operand depend result
operand condit
infin
earli result gener
certain invalid operand
arithmet result
architectur approach

a natur ga pipelin
the purg ga
separ adsorpt zone for the water
nitrogen reject
methan
low temperatur hydrocarbon
liquid natur ga recoveri
carbon dioxid from hydrocarbon stream
carbon dioxid adsorpt
both adsorpt zone
adsorpt
a thermal swing adsorpt cycl
a product ga from the low temperatur

a necessari comput function
the type of comput function
the process of instruct through the function unit
the instruct select unit
the concurr execut of a plural of instruct through a parallel array of function unit
risc core
number of instruct in an instruct buffer
multipl execut data path
instruct set from an instruct store
instruct schedul
function oper
each execut data path
each data path
comput specif of the function unit
an instruct select unit

a neural network processor
the neuron of a multilay feed forward neural network
the neocognitron
the mo analog circuit
an mo analog circuit

a neuron
thi sum
the next cell
the neural net
the alloc of the synaps
synapt cell
parallel control the respect synaps contribut
neural processor
function topologi
function equival of synaps
each respect cell
each cell in the concaten
a unidirect data path
a physic topologi

a new instruct address
trap indic logic i
the system interfac control
the panic trap system
the panic trap indic
the panic trap event
the dcach
the aqueu
synchron reason
pariti error
panic trap system
instruct from the aqueu
incorrect execut of a memori instruct
inaccur result
an alu instruct queue
a panic trap system
a nonarchitectur panic trap indic with the instruct after execut

a new minimum distort block
the refer block
data block against a refer block

a new miss from the slave cach
the tag ram array
the tag pipelin for other oper
the tag pipelin
the index portion of the address
the data ram array
tag pipelin
subsequ sub line onli use the data pipelin
overal data
master slave cach system with de coupl data
loop back flow
flow in the tag pipelin
fast access of the tag ram array
data bandwidth
cach manag oper
bu snoop
a tag pipelin

a new operand specifi
the state silo
the state inform from the silo
the specifi
the respect pipelin segment
the normal sequenc of microinstruct execut
the instruct decord segment
the instruct decod segment decod variabl length macroinstruct into operand specifi
the instruct decod segment
the first execut segment
normal instruct execut
correct of the fault
applic of state silo for recoveri from memori manag except
a suffici amount of state inform
a state silo
a seri of microinstruct in a fault
a seri of microinstruct for each specifi
a queue of regist

a new program
type program
transmiss medium
the program code
the other process
posit in the program
output instruct part of the program
output instruct part
other process part
input inform
an execut of the program
an execut of a program

a new store
valid bit for the master cach
tlb entri
thi fill data
the store queue becaus the store queue act a an extens
store queue for a master slave cach system
store queue entri
store data from the processor
separ byte
maximum bandwidth
line fill
diagnost store
data from the master cach
an execut pipelin of a processor
all cach coher oper
a single physic address field in each store queue entri

a new type of digit map
the terrestri imageri
the aircraft land
the absolut geophys coordin of ani terrestri object in the imag
the absolut geophys coordin inform
the absolut geophys coordin coordin
spatial imageri
real time imag
more terrestri scene
mission medium
latitud coordin
latitud
instantan pictur
ground object
digit record spatial data
digit map
ani secondari media
ani number of seri of terrestri imag
an airborn environ
accur longitud
a two dimension terrestri imag

a next access pipelin stage
the self time pipelin processor
self time pipelin processor
self time data
pipelin processor with self
malfunct of the processor
access of individu pipelin stage

a next branch data
the stream of instruct
the next branch instruct
the next branch data
the branch cach for everi instruct
the branch cach 4
no further read of the branch cach
next branch instruct befor instruct from the target address of that branch instruct
data for that next branch instruct
branch cach 4
branch cach
a target instruct valu ti
a target address valu ta
a pipelin processor 2

a next initi of m the memori map
these novel chang
the repair
the memori map
the ecc
the c/r method increas
the c/r hardwar against random failur
that page
persist copi of the storag map
part of m
no further report of soft excess error
fault toler implement
excess error correct control
error correct method without the assist of a servic processor
ecc logic circuit
an excess error
a storag map
a servic processor
a previou correct in that page
a page in m

a next instruct
the token store memori
the instruct string in order
the data in the data
the arithmet process unit
string of instruct in order
order on the basi of a control
instruct in the instruct
data from the extern memori
data from extern memori
complet of previou memori access instruct
complet of load oper in execut of the instruct
arithmet oper with respect
a start address
a resum address
a plural of instruct string

a next pipelin stage
the like
system for guarante reexecut after interrupt
store buffer if microinstruct
psw
last microinstruct
extern access processing
execut of the microinstruct in the other plural step
except process

a node processor
the packet format
the addit statu bit
part of a packet of inform in a commun network
frame statu byte
decrypt
commun network
addit statu bit

a nois
use in pattern recognit applic
the featur coher
parallel pseudo random number sequenc gener
multi dimension field of pseudo random sequenc
featur correl a input
a pattern

a non integ multipl of anoth system clock
use in a pipelin structur
top box
the second clock rate
the first clock rate
the differ element
system with simultan util of multipl clock signal
system clock in applic
system clock
simultan util
phase inform
other state base logic devic
other process system element
more multiplex in a pipelin structur
certain process system element
a synchron phase detector

a non specul instruct
use an except bit
these except
the specul except
the presenc of an except condit
the except condit
the address of these specul instruct
specul except resolut
specul except
signal from the extra regist
extra except bit
except resolut
except in specul instruct
except bit
cpu overhead i
ani except bit
an origin specul except
an operand from a regist
a specul instruct attempt
a specul instruct
a non-specul instruct which i

a nonvolatil memori
use with a host data
the outboard file cach
the nonvolatil memori
the independ clock distribut sourc
the host interfac adapt
the hardwar interfac
the data mover
redund nonvolatil file
redund copi
portion of the nonvolatil file cach storag
multipl power domain
index processor that control the rout of data signal
independ clock distribut within each power domain
host interfac adapt
file data
file cach data
fiber optic link coupl
data mover at the host
control of storag
cach access control
bidirect bu structur
an outboard file cach
access command
a system interfac
a system for fault toler redund storag of file cach data

a novel data processor
the instruct pipelin from conflict
specif instruct
proprieti
invalid the content
instruct pipelin
branch record
branch predict mechan

a novel instruct
the type of event
state updat
rise
microprocessor with novel instruct
mechan for use by the event
inform in respons
event occurr
event inform
data for use
characterist inform
an out of order microprocessor signal event occurr
an execut unit upon detect of the condit
a retir control circuit of the microprocessor

a novel memori access system
time slot window
the request for access function from the processor
the i/o port
request on control
memori access system
conflict between plural request
address buse
a plural of input output port

a null convent full adder
the adder switche
null convent adder
multipl full adder
multi bit adder with registr
each full adder

a null convent input
wavefront of null
propag
the highest level
the execut time of an instruct stream
no execut
ani idl time of the execut unit
an instruct in a lower level of the stack
a variabl instruct stack
a single input multipl output stack regist
null convent regist file
a plural of null convent storag regist
a null convent regist file

a null convent threshold gate
the threshold gate switche
signal state
distinct current level
current mode null convent threshold gate

a null instruct
the recoveri process
the perform of the data
the oper of the instruct processor
recoveri hardwar
high perform instruct data path
address increment of an instruct address pipelin
a recoveri period after a cach miss

a number m of read port
port for use
number of copi of a gener purpos regist
non interleav read port
n way superscal processor
long word instruct
a number n

a number of data misalign detect circuit
the misalign
page split
one of an execut unit
memori order interfac compon
fault gener circuit of the memori order interfac compon
execut comput system
data on an out of order execut comput system
data against a memori subsystem of the ooo execut comput system
chunk split
cach split

a number of ident process cell
two dimension convolut
such convolut
semisystol format
high speed convolut

a number of individu regist stage
the regist inform
the primari regist storag into the first regist stage of the regist cach
the primari regist storag
the particular primari regist
the older regist inform in each regist stage
the actual regist content
regist cach
queue arrang
often use regist in high speed storag
new regist inform
logic unit for comput
inform overflow from the last regist stage
each regist stage
a regist address tag

a number of instruct counter for each queue
these queue
the instruct of a program into separ queue
the depend between instruct in differ queue
that control issur of instruct from the queue
perform of a processor
instruct in other queue
depend between instruct in the differ queue
depend between instruct in queue
depend among instruct from differ queue
a stall unit

a number of layer
the compon code
the code length
low hardwar complex
effici high rate
each layer
decoder/quant
code in sequenc
block code

a number of mechan
those operand
the readi of a depend instruct for dispatch
the readi logic of a reserv station
the instruct for dispatch
the avail of the sourc operand of a depend instruct
the avail of sourc operand
schedul of depend instruct
maximum throughput
immedi valu
a sourc valid bit

a number of microcod bit
the sequenti execut of instruct
the execut sequenc of the instruct from the next sequenti instruct
instruct flow control for an instruct processor
combin of the microcod bit

a number of node
the standpoint of the cach
the same epoch counter
the epoch that the synch
the epoch mechan
the current epoch
the cach stall
synch oper
share a single cach
separ interv
releas consist multiprocessor system in the presenc
releas consist memori coher
processor until all epoch
processor synch oper
multipl context processor
epoch at each cach
cach multiprocessor system

a number of perform optic comput
uniform data imag onto the beam
uniform data
the subset of the modul
subset of the plural of spatial modul
programm method
one of the modul
data onto a data beam
data imag
complex optic comput
a subset of the modul
a plural of spatial light modul

a number of pipelin clock period
the number of pipelin clock period
the flow of an instruct pipelin in a scalar/vector processor
the condit branch instruct if the branch
no gap
instruct decode/issu
condit branch instruct in scalar/vector processor
branch mechan
a success meet of the branch condit
a probabl
a number of use instruct

a number of util request signal
transport system
the intern format
the end of each util
more address locat
a time slot
a time sharabl run time resourc util control

a number of virtual processor
the router bandwidth
the router
the number of actual processor in the system
mask ani substanti latenc
individu hardwar modul
bulk synchron parallel comput
bulk synchron in superstep of multipl comput step
accord with a bulk synchron parallel process model

a number v in a binari data word
usag of thi format
the number v
the mantissa
the fraction of the mantissa
the fraction f
the expon
f
case that the number v

a one dimension n order discret cosin
the sum of the argument
the addition/subtract procedur
product sum oper procedur
oper method for discret cosin
oper devic
n piec of origin imag data with argument
n piec of dct result
m piec of data with argument
addition/subtract
a posit power of 2 from 2

a one to one map
whilst the natur of the second instruct
the program instruct word
smaller bit size
program instruct word of a smaller bit size
program instruct word of a second instruct
multipl instruct set
instruct word of the first instruct
instruct decod for the second instruct
code densiti
a subset of the first instruct
a processor core 2 via an instruct pipelin

a one-dimension dct processor for product of matric comput
the two dimension dct
the one-dimension dct processor for product of matric comput
the one dimension dct processor
row vector
oper of n-element one-dimension vector for product of matric comput
n data item
column vector

virtual machin monitor
virtual machin
the virtual machin monitor

a oper
user mode instruct
the same point
the primari comput
the failur
the epoch
the end of each epoch
the backup virtual processor
the backup virtual machin
the backup comput
reissue
processor failur
ordinari i/o devic failur
i/o oper
fault toler comput system with shadow virtual processor
failur of the primari comput
epoch
each comput
copi of all i/o
backup virtual machin
backup comput
an epoch
all kernel mode instruct
all i/o oper
all i/o instruct
all i/o devic in use
a recoveri regist

a operand address from the first instruct
the trap queue storag element
the time the result data
the storag of the result data
the plural of shift regist storag element
the old b operand valu
the form a op
the first instruct on the operand data output
the first except
the b operand address from a first instruct
the b operand address
point regist storag control circuit
first instruct b operand address
except data
erron valu
circuit store
b operand address
an operand queue
an except circuit
a trap queue data
a trap queue
a shift regist output circuit output
a plural of storag element
a plural of address storag element
a operand data output from the operand queue
a operand data output

a packet
the diagnost method
the algorithm of the present invent
on line diagnosi in the presenc of node
network system
n node
method for on line diagnosi
link failur
diagnost method for use in an arbitrari network
commun between network node

a page boundari
the tlb translat
the new 32-bit logic address
the memori side
the logic page number
the logic address by a translat lookasid buffer
the last memori access
the effect address gener hardwar
the complet correct 32-bit physic address
real memori locat at physic address
physic address bit from the tlb
parallel with the tlb translat
guess mechan for faster address calcul
guess
clock phase
bit of a logic address
bit from the address comput

a page fault
the recognit of a page fault by the dcu
the pipelin acceler
the page number of a target address of a store oper
the page address
the instruct execut acceler
the digit machin
the complet of the present load instruct
the associ memori
similar oper
room for the new entri
refer the data
recent addit
particular memori access
memori access output a virtual address
instruct execut acceler
digit machin with virtual memori
anoth instruct attempt
an instruct execut acceler
an address match
a small associ memori
a page within the real memori

a page in non volatil memori
the useabl non volatil memori capac
the use bio memori space
the swap of page into the swappabl page area
the page decod
the non volatil memori devic
the high order processor address line
the address space of the non volatil memori devic
the address space
the address boundari
techniqu of the present invent
sever differ form of configur
page 4
page 3
page 2
non volatil memori
input by a page decod
identif inform
distinct page of memori
address space limit
a system bio
a swap area
a page regist
a page of non volatil memori

a page memori
the third unit
the second unit
the record unit
the first unit
the bit map from the second unit
raster imag processor for all point address printer
overal coordin of the unit
all point address printer
a raster imag processor
a parallel process pipe line

the printer video processor
the printer control
pixel modif
other peripher devic
data from memori under the control of the instruct processor
data for transfer
bit/byt mirror
an intern memori interfac
an integr part
an instruct rom
an i/o interfac interconnect the printer control with an i/o
a vlsic page printer control
a risc instruct
a printer video processor
a printer through a video port

a page printer control
the special function
circuit of orthogon rotat
a single chip supercalar microprocessor with graphic function unit

a pair of arithmet logic unit
thi arrang stream of data
thi arrang control flow calcul
the tandem arrang of arithmet logic unit
the second arithmet logic unit
the input of the second arithmet logic unit
the gener purpos regist
the data transform capabl of a single arithmet logic unit in a data processor
tandem relat between an input
procedur boundari
memori stream of data
data transform at everi moment
data from the regist file
a second input port
a result procedur call paramet
a pair of input port

a pair of multiplex in an input portion of an adder in a data
thi control oper
the structur control oper of the multiplex in accord with a regist conflict
the regist conflict control
the regist conflict
the preced instruct
the immedi data
input the data from the immedi data
immedi data
execut of address conflict instruct
calcul of memori address
an idl state of a pipelin
a specif regist
a regist conflict between a regist
a preced instruct

a pair of multipli
the variou section
point numer processor
control data path
a seri of decod
a pair of parallel accumul

the smaller regist of the vector regist
the m element of the vector
the element processor
smaller regist
parallel vector processor
m element of the vector
element processor
each smaller regist
an element processor
a plural of smaller regist

a pair of vector
vector element in parallel fashion
the process of the m element of the n element vector
the perform of the parallel vector processor
the n element vector
result of the process
a pair of vector regist

a parallel configur
the element of a single vector
each vector regist of a plural of vector regist
a result regist
a result of the process in a result regist
a result of the parallel configur of the plural of unit
a plural of unit

a parallel process type processor system with trap
the processing of the instruct
the processing
the lower of the clock frequenc in the system
stall control function
parallel process type processor system with trap
a possibl for an occurr of an except in the execut of the instruct

a parallel safe instruct recognit network
upper limit
underflow except
the simultan test of both operand expon
the examin of the expon of each operand
lower limit
float point processor overflow
float point processor
each expon
a simple symmetr test
a safe instruct recognit method

a parallel sort system
the amount of commun
parallel sort system

a parallel vector processor
vector register/el processor configur
third success m element of the n element vector
the third success m element of the n element vector
the second success m element of the n element vector
the same vector regist
the process of the second element
the first success m element of the n element vector
the first success m element of an n element vector
the element of the vector
the element of a vector
the complet of the process of a first element
storag in the smaller regist of the vector regist
storag in the same m smaller regist
storag in the m smaller regist of the vector regist
storag in the m smaller regist
m smaller regist
high perform parallel vector processor
a smaller regist
a second element

a parallel viterbi
viterbi
the tbsr from a comparison of binari digit signal
the tbsr
the state counter
the signal reconstruct
the first group
signal sample index
short symbol
is54
gsm
each signal sample in the second group in accord
each signal sample in a first predetermin size group
doppler error in a wireless commun system
doppler error
an estim of the doppler error in accord with the parallel short traceback
a viterbi traceback
a traceback shift regist
a state counter
a signal reconstruct
a second predetermin size group

a parallel/pipelin processor
the valu between the base compar
the state variabl
the compar tree
such valu
processor for dynam program
optimum transit for success state space cell in a pipelin fashion
optimum cost
optim problem with dynam program
a transit
a serpentin memori arrang
a plural of parallel compar at the base of a tree of compar

a paramet memori
the tag memori output
the paramet memori
the necessari inform
the necessari calcul
the appropri fifo
statu bit for each paramet
signal r
processor node architectur
output inform from the processor
input inform form
inform from the processor
fifo regist
data paramet
data flow machin for data
b paramet
an opcod memori
an intern fifo
a target memori
a tag memori

a part of an instruct
unit output a step code
unit output a first step code
unit decod
the result a a fuuther step code
the plural of step code
the plural of address extens field
the operand specifi of the instruct
the operand specifi into sequenti step code
the base valu of the address
the base valu
the address extens field
the address calcul unit
operand address calcul in a pipelin processor
more step code
anoth step code
an operand specifi
an instruct oper execut unit
an arbitrari number of address extens field
an address calcul unit
address extens field
address calcul of the operand
a single operand address
a single operand
a second step code

a partial number of instruct within the clock cycl
the resourc pointer
the resourc buffer
the resourc alloc pointer
the remaind of the instruct
the rat buffer
the partial stall
the issuanc of new instruct
the instruct issue compon of a processor
the full stall
the clock cycl of the deassert of the partial stall
the clock cycl of the deassert of the full stall
that clock cycl
resourc pointer
processor stall condit
partial stall
instruct sourc a larger regist width than the regist alia
full stall
detect of a partial stall
detect of a full stall
buffer resourc
anoth stall condit
ani buffer entri within the clock cycl
a retir entri pointer
a result of variou stall condit
a partial width data depend
a partial stall

a partial product gener circuit of each stage in a multipl array
the second half of the clock
the partial product gener circuit of each stage
the intermedi result data
the first half
the final accumul addit result
the bit of the multiplicand data
the bit of multiplicand data
the accumul result in a latch a intermedi result data
the accumul addit circuit of each stage
sum of product calcul devic
partial product on the basi
number of bit of the output from the accumul addit circuit of each stage in a latch
number of bit of an output from the accumul addit circuit of each stage
multipl devic
low order bit of multipli data
high order bit of a multipli
half the calcul
half necessari multipl
cycl of a clock
bit posit of the latch
bit of an output from a latch
an output from a previou accumul addit circuit
an accumul addit circuit of each stage in the multipl array

a particular applic
the self refresh oper of a dynam memori part
the self refresh counter
the self refresh control circuit
self refresh oper
row address for self refresh cycl
row address counter
complet of a self refresh cycl
an oscil
a self refresh counter
a self refresh control circuit

a particular clock phase of a pipestag
the srf
the scope of the present invent
the low phase of a clock cycl while the srf
the high phase of a clock cycl for differ instruct
the agu in altern clock phase
the abov phase relationship
separ instruct
segment regist file
resourc conflict over the srf read
pipestag of the present invent
oper of the srf
differ pipestag of the pipelin
differ pipestag
anoth clock phase of anoth pipestag of the agu pipelin
an effici pipelin
a same clock cycl

a particular counter within the perform monitor
perform monitor
anoth counter within the perform monitor
all code point for each perform counter
a particular event

a particular data item
uniqu identifi
the same identifi
the identifi of the plural of data item
the data in the data item
ident data item

a particular data processor
the total data byte
the number of byte
the first operand address calcul
the first operand address
the address calcul step
subsequ data
second operand address
each transfer
data processor in the present invent
cycl of the pipelin control
a transfer out address
a transfer instruct
a transfer in address
a plural of number of transfer

a particular group of free regist
use state
the output of the alloc regist
the alloc regist address
dynam regist alloc
assign for each new task in respons
an alloc regist
an address for a regist alloc memori
allocat regist

a particular high level order
the low level order
the graphic processor load appropri bit pattern
the gener processor until the latter
the front of screen perform
pipelin display control
pipelin control logic control the pipelin
order by recomput
main processor graphic oper
main microprocessor
low level graphic order from the gener microprocessor along a pipelin
high level graphic order
graphic processor access
graphic imag from a host processor
graphic hardwar
gener control
certain low level order
buffer store
buffer for subsequ display on a cathod ray tube monitor
all point

a particular manner
uniqu architectur arrang
the oper of the fpu within the context of a gener purpos digit comput system
the oper of the fpu
the fpu commun with main memori
the control block
oper of the cpu
mantissa relat calcul
mantissa
interconnect therebetween
exponent/sign relat calcul
exponent/sign function block
concurr exponent/mantissa oper

a particular pipelin stage
vacant stage
the lack of data from an earlier pipelin stage
the cpu instruct
pipelin bubble compress in a comput system
bubble compress
bubble
ani use work
a stage in the pipelin

a particular power
the wait state request
the processor that the peripher i
the isr
that power
state until the peripher i
return from the isr
reset unit
bit in thi regist
a softwar programm
a processor request
a power

a particular process stage
the particular track regist
the particular track indic
the particular process stage
the particular physic regist
the id
physic regist of the processor
instruct for the processor
id
ac
the segment access indic
the processor in respons
the execut pipelin of instruct
segment of system memori
locat within the segment
gener of the except
an address pointer of the processor with an address
a segment of the system memori
a segment load instruct
a segment access indic
free regist
each stage of an execut pipelin
combinatori circuitri
avail of the physic regist
an avail
all particular track indic of the id
a valu from a particular physic regist
a regist translat system
a particular track indic of a particular track regist

a particular sound waveform
volum bit
variou process stage
the sound waveform of each audio channel
the plural of data for each audio data
the data sample
the audio processor in a serial manner
the audio processor act
the audio data sample into a plural of data
the audio data sample from each audio channel
the audio channel system
number of audio data sample
each audio channel
audio channel system
an audio processor
an audio output
an audio channel system
a volum level of each audio data
a total audio output
a sound waveform in a comput system
a plural of volum bit
a plural of audio channel

a particular transfer
the storag transact
the next subsequ address
the bu in order
the address transfer
system with a plural of processor
an address transfer
an address on the bu
a seri of inform transfer interv
a plural of data processor unit

a particular type of messag from the host
the host download
the case for prior art
system with a messag pass architectur
pattern
transpar polygon
thi memori alloc scheme
the polygon data
the frame buffer for everi polygon
that pixel
sub pixel sampl pattern
polygon edg without the degrad of imag qualiti
pixel data for display
per pixel heap
frame buffer memori requir
filter without pixel to pixel cross commun
convent comput graphic system
comput graphic system with adapt pixel multisampl
an adapt pixel multisampl
just rectangl
graphic subsystem with slaveabl raster
bitmask

a particular watchpoint
watchpoint inform
watchpoint
the watchpoint inform
the watchpoint
the processor state
the histori buffer
processor state valu at the time
more watchpoint
more counter
increment/decr inform
histori buffer
each instruct of a program
breakpoint inform
breakpoint in a data
associ with the processor state valu

a passiv devic
the mode of oper of the data processor
show cycl
real time track of control function
emul tool
distinct mode of oper
both read
a similar format

a patch
the subsequ patch of the sourc imag
the arithmet process pipelin of the processor by execut
store unit of the processor
store pipelin of the processor while the arithmet process pipelin
store pipelin of a load
retriev data
pixel data for convolut
more arithmet process pipelin of an arithmet process unit
graphic imag convolut
excess cach
convolv the pixel data
arithmet oper on the pixel data
addit oper convolv multipl pixel
addit oper
a subsequ patch of pixel from the sourc imag
a secondari index
a primari index
a patch of pixel from a sourc imag

a pathway
those memori
the memori access inform
the coupl of processor
the bu unit
setup befor the bu cycl
respect memori
other bu unit
multipl simultan access request
multipl memori
memori with other processor
high order address line
each bu unit
each bu cycl
dynam bu reconfigur
differ access
bu unit with arbitr
access differ memori address space
a specif embodi

a pattern gener
valu into the circuit
the pseudo random number sequenc
the pattern gener through the compare/stor function of circuit
the pattern gener
the control of circuit
self re seed linear feedback shift regist
self
pseudo random number with minim logic
mani pseudo random valu
a test control
a pseudo random test bit stream

a pattern recognit engin
voic recognit system
use of a privat memori
these pipelin
the present invent system
the perform of program
the pattern recognit engin
the main cpu
recognit procedur
quick access of the librari pattern
prototyp pattern
privat pattern memori
method of pattern recognit
markov model procedur for pattern recognit
gener purpos comput system
each pattern recognit engin for librari storag of refer
commun between the cpu

a peculiar problem of an intra instruct read conflict
valu of specifi regist
thi initi valu
the time that the execut unit
the time of instruct
the proper initi valu
the instruct decod into a special irc mode
the initi valu of the regist
the excel unit becaus regist data
specifi for the current instruct
regist data
multipl specifi of a variabl length pipelin instruct
multipl specifi in a variabl length instruct
instruct by the instruct unit
an intra instruct read conflict
an effici method
an autoincr
an autodecr specifi
a regist specifi

a peripher address bu portion of the pbu
these access
the time of the second access
the piu priorit
the piu
the pbu by the piu
the pbu
the order of the read instruct
the least critic read
the core regist
such case the piu insert proper pipelin stall
state pipelin stall
stall signal
regist in the core space
read oper on a first sourc
peripher modul
peripher interfac
oper on a second sourc
oper between processor
microprocessor core
core regist
all read access from the core regist
access onli stall the pipelin
access across the pbu
a peripher interfac unit
a peripher data

a peripher control
the start of the parallel process
the peripher control
the parallel process at the main processor
the main processor into a program
the instruct in a pipelin mode
the instruct from the coprocessor instruct memori
the coprocessor upon complet of the dma data
the buse with the main processor
system for the main processor
peripher devic for sequenti control
parallel with the execut of the main processor
instruct execut of the coprocessor
data memori by a direct memori access
an coprocessor instruct memori
a work area
a sourc program for control of the i/o
a sourc instruct memori
a programm control

a peripher processor over a fiber optic interfac
the throughput of the interfac
point to point link
physic layer control
frame format
frame control logic coordin
fiber optic interfac
fddi
error free data transfer
dual fiber
data into frame for transmiss over the interfac
data in a point to point implement
asynchron mode

a phase differ of a half of a period of a basic machin cycl
vector data element sequenc
vector data element
the vector data element sequenc
the respect vector data element
the respect modul
the ram array
the basic machin cycl
ram array
input/output oper of vector data on a plural of vector regist in a parallel fashion
a vector data element sequenc
a sequenc of odd number vector data element
a sequenc of even number vector data element
a plural of load/stor pipelin from a plural of arithmet unit

a physic system into the memori of a multiprocessor
the origin of the element along the other axi of the matrix
orthogon axi of the matrix
non zero element into memori
multiprocessor for matrix manipul with special handl of diagon element
matrix element
finit element analysi method
equat
ultra highampl rate system
ultra high bandwidth
time skew input data
techniqu vector
special purpos chip set
snr and/or
signal reconstruct
no matrix invers
measur from data
low cost real-tim hardwar that i
least squar optimum snr output data from a plural
high snr
fast high-sign to nois ratio equival time processor
et
equival time
an implement of the techniqu
all oper in a vector
diagon element of the matrix
a transpos vector
a plural of the processor

a pick queue
the tag address
the pick queue
the pick
the coordin counter
pick inform of the order
non hierarch graphic data model
necessari pick inform in a pick queue
each graphic
detect method
all inform through the pipelin processor
access the tag regist
a pick tag

a pipe lock signal gener section
the pipelin until further process
section with a plural of instruct
pipe lock signal
data depend between success instruct
control section with a plural of instruct
control section
a processor with a plural of oper pipelin

a pipelin address
the use of handshak signal
the pipelin bu permit a free flow
the pipelin bu
the particular process task
n pixel subimag block
imag processor with free flow pipelin
data in parallel among the compon of the system
data among the compon
an intens processor
a single address

a pipelin comput architectur
the same portion
the next task
the next tank
the main microengin a the main microengin
the main microengin
the instruct prepar unit hardwar
the execut microengin
suppli argument
second microengin
each microengin
differ portion of an instruct
current routin
an instruct prepar unit of a pipelin comput system

a pipelin comput control store with separ memori segment
the memori chip
single microinstruct
sequenti multipl microinstruct
no delay
multipl microinstruct with condit branch
multipl microcod instruct sequenc
mode at the maximum pipelin rate
microcod memori bank
lookahead
the set of risc instruct
the processor architectur
the execut of program instuct by an emul
the emul
foreground like oper
foreground instruct stream
each program instruct
each next program instruct
distinct instruct stream by the dual integ
background like oper
background instruct stream
an interpret emul
an dual integ
a wide rang of differ class
clock delay

a single machin cycl
the oldest instruct
store/load forward circumst
sourc operand depend analysi
rapid pipelin recoveri for a microprocessor
precis recoveri
other store/load conflict
memori access instruct
instruct in out of order sequenc
ani execut

a pipelin disturb
the special state of the second instruct
the special state
the final state of the second instruct
the final state of the first instruct
state of the second instruct
a special state a a final state
a pipelin oper control method

a pipelin function
the result of the extern access type instruct
the result of extern access type instruct
the read buffer regist
the data into a regist
store inform
processor with pipelin
devic store data
an extern devic by the process of an extern access type instruct word
a regist in a regist file
a read buffer regist

a pipelin instruct processor
the target instruct data
the histori data
the execut of branch instruct
histori data
branch target instruct in a cycl
a plural of branch instruct

a pipelin length
the second function element
the respect path input
the process of second operand data in a second of the function element
the pipelin length of the first function element
the path input
the function element
program instruct initi
process of operand
pipelin length
function element
first operand data
differ pipelin length
complet of the first instruct

a pipelin of a comput system
the statist of the instruct
statist of properti of instruct
state inform of the system
state inform from a subset
a profil record a sample

a pipelin of the processor
the memori until the data
memori prefetch oper in the program
memori prefetch oper
memori prefetch instruct
latenc of instruct of the program
latenc in a program optim
hardwar while the instruct
execut of the program
data of a memori oper
a request for data
a program optim

a pipelin processor in a graphic comput system
the subsequ stage in the pipelin processor
the subsequ process stage
the stage in the pipelin processor after a request from a prior stage in the pipelin processor
the sequenti natur of the pipelin processor
the particular mode
the adapt cach
pixel engin pipelin processor data
no lag time from memori access
maximum perform
an intellig replac polici
an adapt cach memori
advanc the data
a subsequ stage
a prior stage

a pixel address
these refer
these pixel
the textur request
the textur data
the textur cach
the latenc of a textur block
the appropri textur block
textur data in environ with high latenc in a graphic
textur data in a graphic
textur block refer
textur block from memori
output pixel
memori with high latenc
color data
block of textur data
anoth implement
a textur request
a textur cach
a textur block
a raster raster each geometr primit a the necessari textur data

a pixel arrang scheme for a high resolut graphic
video ram
thi scheme
high resolut graphic display organ
capac of vram
a temporari memori in a convent system

a pixel data stream
transit data imag processor
the zero between the edg code
the subject matter of u
the subject matter of thi applic
the sequenc of gener
the sequenc of avail
the scanlin number
the present assigne
the non transit period between transit
the non transit period between edg code
the memori map in ani sequenc
the map in display order
the edg code
the continu display
the address in the map
pixel number of the edg in the display of the imag
patent applic ser
non zero code
may
intens control voltag
gate advanc
edg data code
edg code into the latch
edg code
each edg code
control voltag
control other display featur
composit display devic
color scale
a random access memori map at address

a pixel filter
the vlc decod
invers cosin
dequant
both gener purpos
both control inform
a video output unit
a variabl length code
a tabl driven state machin

the sequenc of most gener applic
the respect pixel
the proper color intens for each visibl pixel
the observ
real time oper
logic enhanc pixel within an imag buffer
logic enhanc pixel memori cell
inexpens raster scan type graphic system
each success polygon
custom vlsi chip
calcul at everi pixel
all pixel within the polygon
a typic implement

a pixel of the display
same pixel
each polygon in the imag
each cell of the imag buffer
calcul of the pixel color
a processor at each cell

a pla
user program execut
these sequenc
the pertin intern regist
the intern regist
the function of the major of the regist
test the major
single step execut for debug purpos
self test microcod
program in extern memori
other pipelin architectur featur
logic unit of the microprocessor
intern regist
independ address
data path in the machin
control microcod
ani locat in memori
ani extern memori locat
an extern bu arbit for use of the comput in a multiprocessor network with a common bu
address pla
a self test sequenc of instruct

a plural n of instruct thread
the princip processor compon
the hybrid architectur
sequenc of oper on instruct from the plural n of instruct thread
multipl set of regist
multipl instruct thread
hybrid process method
concurr multipl instruct thread
a time divis manner multipl program instruct thread
a single pipelin processor

a plural of address pointer
the storag capac of the result area
the sourc element of the problem express
the result section
the result gener
the result express into the environ area of the memori
the result express into a result area of the memori unit
the result express from the result area of the memori unit
the result express from the environ area of the memori
the problem section
the environ area
the control unit of the present invent
storag locat from the result area of the memori unit
storag locat from the environ area of the memori unit
sourc element of a problem express
signal commun
result gener
pre identifi sourc element of the problem express
lambda calculu express
environ section
applic languag code
a transfer unit
a signal bu system
a result express
a reslut section
a problem section

a plural of apparatu
vector rotat without trignometr lookup tabl
vector rotat through a plural of angle
the throughput of an fft
serial add/subtract stage
prior art digit processor
number of point
increas the throughput rate
digit word
cordic techniqu
cordic fft processor

a plural of architectur regist
thi abil
the same architectur regist
the appropri valu increas data processor throughput
request for the operand
instruct stall
an architectur regist

a plural of branch target address and/or
the control field
that code
simple hardwar
other applic
onli branche
instruct code at a branch target address
an execut unit within a single clock
a plural of branch target instruct for branch instruct

a plural of configur file
the programm logic block arithmet unit
the programm logic block address gener
the programm logic block address
seri of arithmet logic oper on the data in the data
multibu sequenti processor
each configur file
data in the data
configur in respons
an arithmet hardwar configur file
an address gener hardwar configur file
a seri of oper code
a reconfigur sequenti processor
a programm logic block arithmet unit
a programm logic block address gener
a plural of reconfigur logic oper on a plural of data set

a plural of control direct
the tag regist file
the physic regist file
the instruct operand
the current top of stack regist
stack manipul
an instruct execut
a to address gener
a tag regist file
a stack regist file
a stack organ
a pointer tabl regist file
a pointer tabl address gener
a plural of pointer tabl regist store physic regist address

a plural of control line
undirect
the six bit code bu address the input/output devic
the local storag regist
the execut control store
the central processor on the common poll
storage/regist transfer
request common poll
register/regist
more input/output
local storag data transfer
execut control storag
data from the input/output devic
control channel
byte manipul
bu microcomput architectur
both cycl
an execut control
all storag devic
address modif
a six bit code
a plural of local storag

a plural of data input
video overlay system
the input/output control
paramet of the devic
inform on a pipelin with a video imag
graphic gener
display system for a pipelin video
data collect
automat pipelin data collect
an oper input

a plural of data path
the use of thi techniqu
the execut of a vector instruct by the vector function unit
the execut of a vector instruct
the configur of the pipelin
run time configur pipelin
multipl oper upon set of vector data
configur valu
a single short vector instruct
a scalar regist
a plural of parallel pipelin

a plural of electr function unit
the statu indic
the single cycl instruct
the single clock cycl instruct
the processor a the new oper status
the previou oper status
the pipelin latenc
the multipl clock cycl instruct
the current oper status
the control unit further control the statu indic
soft programm single cycle/pipelin micro program control system
single clock cycl instruct
propag time
new oper status of the function unit
multipl clock cycl instruct
current oper status after each clock cycl
an open loop mode
a statu memori store previou oper status of the function unit
a statu indic

a plural of group of bit
the plural of data in respons
the parallel process microprocessor
each group of bit
a regist file with a plural of function unit

a plural of histori bit
vt
vh
vector move instruct in a vector data
the vnmvh instruct
the temporari use of a regist in a softwar code
the least signific bit of vector regist
execut of vnmvh instruct
execut of the vnmvh instruct
element in the vector data processor
a vector data processor
a substanti number of instruct
a set of a statu bit

processor element
each processor element

a plural of ident processor element
the plural of ident processor element
storag resourc
parallel processor system
natur concurr in the basic block of the program
natur concurr
logic processor number
instruct basi
execut state inform from prior oper
each instruct in each basic block
differ processor element
an instruct from anoth context through use

a plural of initi packet
the time of a clock
the shift regist at the proper time
the rang of intern clock signal phase
the phase of the intern clock signal i
phase of the intern clock signal i
normal oper of the memori devic
initi packet
each initi packet
dynam random access memori devic
an evalu circuit
a transit of the intern clock
a single phase of the intern clock signal i

a plural of instruct in a sequenc
that condit regist
single cycl dispatch delay in a multipl instruct dispatch mechan of a data
more processor for execut
bit in a condit regist
a single comput cycl
a previou instruct execut
a plural of the instruct

a plural of instruct in an instruct sequenc
the execut result of the instruct sequenc
the condit of the condit branch instruct
the condit branch instruct and/or instruct
specul execut processor
parallel instruct
an instruct type
an instruct parallel issu devic
a type of a condit branch instruct
a specul execut processor

a plural of instruct regist
stage of a plural of instruct
parallel by the plural of arithmet oper unit
machin cycl at a time
arithmet oper unit of the same number

a plural of less signific program counter bit valu
the less signific program counter valu bit
program counter valu in a multipl pipelin processor
program counter valu
program counter updat mechan
program counter circuit
less signific program counter valu bit in addit
a single less signific program counter bit valu

a plural of memori cell
well defin way through a dynam bi direct switch system
topolog distribut memori multiprocessor comput
the topologi of data distribut
the multiprocessor comput
similar memori cell
nearbi partit
each slave processor
dynam variabl
differ respect one of the memori cell
broad class of problem
analysi of data
advantag of symmetri
access by the slave processor
a way that no data flow conflict
a plural of non directli commun slave processor under the control of a synchron

a plural of memori devic
variabl tick delay devic
the cross bar
output oper
data therebetween
cross bar
a sourc of address for the memori devic

a plural of modul area
synthet apertur radar data
optic analog data
multi cell spatial light modul
multi cell light detector array
light into signal
conjunct with space
complex data element
complex data
both bipolar
bipolar

a plural of multistag execut path in a comput system
the posit of the instruct in the sequenc
the execut path
regist in a path
parallel instruct execut with operand avail check
execut path
complet of execut
a success of instruct

a plural of one bit processor element
thi control circuit
the power drain
the portion of the circuit
nois reduct control circuit
method for a synchron vector processor
data transfer control circuit with a sequenc circuit
data into a memori
control subcircuit
a power drain

a plural of pointer
these error condit
the time the instruct
the tag with a storag locat in a first activ instruct data structur
the storag locat that move in respons
the storag locat in respons
the instruct activ
that point
that movement of the pointer
instruct pointer
instruct in the data structur
instruct along the data structur
instruct activ statu chang for each instruct
error condit for ani instruct
each locat
each instruct at the time of issue
an activ data item
an activ bit
a uniqu identif tag

a plural of polygon after the polyhedron
the polyhedron
the comput graphic system
polyhedron
a realist display of the polyhedron
a polyhedron

a plural of predecod bit for each instruct byte
the variabl byte length instruct
the statu of the start bit
the predecod unit predecod the instruct
the predecod unit
the predecod tag
the predecod inform from the predecod unit
the plural of predecod bit
the mean of the function bit of a particular predecod tag
the instruct align unit
storag within an instruct cach
small number of predecod bit
small number
predecod unit
level of logic gate
larg amount of predecod inform
issue posit within the superscalar microprocessor
instruct align
high frequenc of oper
few pipelin stage
each instruct byte
a superscalar microprocesor
a reduct in the size of the instruct cach
a predecod unit
a predecod tag

a plural of rang of element
the circuit of the present invent
problem in a comput system
maxim element level overlap
instruct in individu pipelin
instruct in a logic manner
data conflict in a multipl processor comput system
data conflict
data access by other processor in the comput system
a rang of element

a plural of raster scan line of pixel valu
the neighborhood window for analysi
plural of success pixel scan line
pixel valu from the ram
neighborhood transform stage
line storag devic
imag analyz with variabl line storag
differ raster scan line length
a transform output a a function of the pixel valu

a plural of requestor
the transmiss of the read address check bit
the read address bit
that control the read
partial write of data
load read address stack
interv from the receipt of an initi load address
each set of read address check bit upon the occurr
each set
certain one of these signal
an error detect circuit
address stack selector read out read address check bit
address stack
address check bit upon the occurr
address check bit stack control
address check bit gener
accord with read
a set of check bit
a read address stack selector
a read address stack
a read address circuit

a plural of serial neighborhood transform pipelin
the number of pin for each stage in the pipelin
the number of interconnect therebetween
such manner a parallel pipelin imag
segment of the imag matrix between adjac processor in a manner
pixel data on the edg
imag matrix
circuit form
adjac segment

a plural of storag level
zero cycl multi state branch cach predict data
the storag level in the plural of storag level
the fact that the branch cach
the branch in execut flow
state see fig

a plural of subcircuit
the subcircuit
the assert of a control
control power manag

integ oper
program control oper
multipl launche
multipl execut resourc of the central process unit
multipl execut of the instruct within a central process unit
memori refer oper

a plural of success stage
the plural of success stage in the instruct pipelin integ operand
the plural of success stage
the integ result
real number oper
integ result
data path in a single instruct pipelin processor
an integ result
an integ oper

a plural of virtual processor
the form of a side
the case of linear predict
the case of direct l fir filter
superlattic structur
superlattic for the product of linear predictor
retriev structur
more real processor
intermedi variabl
filter coeffici
direct predict coeffici
direct least squar finit impuls respons
a storag
a side fed superlattic superladd structur

a pm instruct
unit of the comput system
thi manner data
the second level cach pipelin
the second level cach
the intervent
the execut of the fa instruct
that execut of intervent
split level cach in a multi processor system
processor in the comput system
oper of cach memori access instruct
intervent
deadlock prevent scheme
deadlock in a multi processor comput system
behalf
an intervent
an instruct in the second level cach
an fa instruct
a word writabl second level
a second level cach pipelin
a possibl miss

a portion of hardwar system area
those millicod instruct routin
the read onli store address in the regist in parallel with the normal cach directori lookup
the read onli store address
the millicod read onli store
the directori lookup result
the absolut address of the instruct
simple millicod
read onli store a part of cach store
hardwar system area address
common applic workload
a small set
a read onli storag

a portion of the virtual address with a portion
virtual memori in a comput system
the translat tabl entri
the translat descriptor
the correl of virtual memori address
portion of a virtual address
physic memori address
a variabl group of virtual address
a translat descriptor for the virtual address from the tabl in main memori
a softwar algorithm

a posit within the macroinstruct gener micro oper flow
uop sequenc
uop insert event
the uop insert unit suppli signal
the uop insert event
precis time of a fault model
later pipelin stage
flexibl mechan for earli pipelin stage of a microprocessor
a uop insert unit
a supplement micro-oper sequenc into a macroinstruct gener micro oper flow
a supplement micro-oper flow into a macroinstruct gener micro oper flow

a possibl except
the float point pipelin
the float point microinstruct
fp instruct in an execut stage
float point instruct pair
ani except

a practic tool for global visual of comput oper
the number of time that a same address
the full execut
the execut of all micro instruct resid in the microstor
the durat
no limit
microstor refer
microstor address
long term event
each address of the microstor
all possibl input paramet

a preced basic block in an instruct group
the function of the comput
the degree of parallel of instruct
parallel in the order of an instruct code
parallel i
basic block
an instruct in the preced basic block

a precis except
the handler
the data unit
the check
suffici inform
special input operand check
special buffer
output result format
mechan if the output result
each type of except
data unit for use in a data processor
an imprecis except

a predict inform buffer
the predict inform buffer
predict of a branch instruct
predict inform
cycl of the branch instruct
branch predict of the branch instruct
branch predict from a regist file
accuraci in branch predict by refer
a same time
a result of oper of an instruct pipelin in accord with the predict inform

a predictor circuit
total memori requir
the final stage
tabl entri
synchron of depend instruct
such depend
entri for each instanc of potenti depend
data specul circuit for parallel process comput
data on previou instruct

a prefetch
writeback instruct
use of the scratch pad
the program order
resiz
relocat memori scratch pad a a cach slice
non block instruct
multipl line of data from the scratch pad
load multipl line of data from extern memori into the scratch pad
base address of the scratch pad
a writeback instruct
a re sizabl softwar manag fast scratch pad
a processor regist
a prefetch instruct

a prefetch control in the ipu
word instruct
the usag by an instruct sequenc of the instruct word
the requisit number of instruct word in the instruct queue
the movement of the instruct pipelin
the instruct length/pipelin movement
the actual number of instruct word
number of instruct word
instruct word from the instruct queue
instruct unit everi clock cycl
decod the instruct for execut oper
an instruct queue in the ipu
an instruct cach of the data processor
a sequenti prefetch method
a sequenti instruct prefetch unit

a prefetch regist
the number of pipelin cycl between complet of execut of the branch instruct
the minimum number of pipelin cycl
the head instruct of the target
the execut of a branch instruct in an instruct pipelin
earli instruct

a prefix state machin
the prefix state machin
the microcontrol
the improv
prefix
microcod vector for the instruct
microcod vector
condit jump instruct in a single clock in a comput processor

a presence/abs of data depend
the data of the regist
sourc operand data
select of the select circuit
pipelin risc
logic unit in the memori access stage
logic unit in the execut stage
load data from the data memori
load data from a data memori
instruct for pipelin stall prevent
execut of thi oper instruct in the memori access stage
data depend between a load instruct
an oper process unit
an oper on the sourc operand data
an oper on data
an oper instruct

a primari cach
the setup time for memori control signal
the secondari cach data
the origin version of the address bit
the memori share a common data
the memori refer
the comparison of the cach data tag
the cach tag store
the bit of the address
the appropri signal
tag from the cach tag store
secondari cach data
secondari cach access
page mode
memori share a common address
memori access in page mode access system
main memori address replay
cach tag store
a secondari cach data

a prioriti of a store access
vector process data in main storag unit
the vector process data through the read
the vector process data
the store of the vector process data from the vector process data
the store of the read data in the main storag
the read of the vector process data from the vector process data
the prioriti determin
the main storag unit
store control unit
an access time
a store data align circuit for a pipe line structur

a processor for an fm/cw sensor
the sweep period of the sensor into a number of subsweep interv
the subsweep interv
the reflector
rang bin of the fm/cw sensor footprint
power within a multipl of frequenc window
fm/cw sensor processor for target recognit
a spectrum analysi of the power measur in each frequenc window

a processor instruct
variabl valu
the branchless absolut valu instruct
the absolut valu of a variabl
processor branch instruct
color vertex valu
color vertex data

a processor mode
the test mode
the test instruct
the processor mode
the processor instruct
the oper mode
the content of the plural of intern regist
processor instruct
microprocessor with instruct execut control unit
intern function block
instruct under the test mode
instruct under the processor mode
instruct from separ path in test mode
diagnosi of respect function block
content of a plural of intern regist by test interrupt
a test mode

a product sum
the provis of the input
the processor element
the output of the regist file
the output data of the line memori
such constitut
select of imag data
line memori
gener abil for the imag
data in an arbitrari process step
an arbitrari process step of the other processor element

a profit valu
use an assign
the variabl in a program
the resourc success relat
the relat between assign
the part of the program
the assign with the highest prioriti level
standard an evalu of a reduct in transfer instruct in the object code
resourc element with a lowest use cost
resourc element determin unit
prioriti level
other assign
highest profit valu
each assign
combin of variabl
assign
an assign resourc element
account the use cost
a same resourc element

a program control type processor
the vector pipelin instruct
the program control
the pipelin oper for the data
the end
the content of the vector pipelin instruct
program control type vector processor
output a start
complet of the pipelin oper
an oper of the data processor
accord with a vector pipelin
a vector pipelin oper for a seri of vector data
a vector pipelin instruct

a program except
track of the memori region
the out of order load oper
the incorrect execut of a load oper
the execut of store oper into region
out of order load oper
dynam reorder of memori oper
apparatu region base detect of interfer
an apparatu that map the memori address space of the comput system into region
a region base map

a program histori
the ram without interfer with the use of the ram by the other function that access
temporari storag queue
task inform
queue regist
program histori
branch type instruct address

a programm digit signal processor
the size of the delay
the inform spectrum
stationari interfer cancellor
combin of time delay
cancel filter around stationari undesir signal
automat gain control at the output of the circuitri
a stationari interfer cancellor

a programm gener purpos digit imag
the shortest possibl overhead time
the greatest number
more pipelin
each chain
chain
a serial connect of a convolut

a programm logic structur
the single instruct multipl data
the reconfigur processor architectur of the invent
the reconfigur architectur of the present invent
the progress of a comput
the pipelin function into the alp
the oper of the alp with other inform
the implement of program specif pipelin function
the construct of low cost
the configur process
sensor data
reconfigur comput architectur for use in signal process applic
high perform parallel process system
arithmet process unit
architectur concept
ani number of time
an extend field programm gate array
an architectur for inform
an adapt logic processor
a reconfigur pipelin instruct control

a programm prioriti encod
variabl in the prioriti
thi unit
the start of a program segment
the prioriti encod
the bit posit of the input regist
the bbd instruct
the bbd function
test type routin
system requir
subject bbd unit
select of branch routin
programm prioriti branch circuit
prioriti select stack
poll
perform of prioriti branch oper
parallel with other system function
multipl differ class of condit
more effici execut of program branche
locat of branch target instruct
inform into the branch address
differ set of bit
content of the branch address stack
branch address select oper
ani contemporari process system
an address from the stack in accord with the posit in the input regist of a highest prioriti
an activ request for instruct
a stack of select control regist
a special purpos circuit unit
a special bbd instruct
a single clock cycl of the system

a programm processor
use in an automat retarget code gener
the processor a a single graph with vertic
the instruct set of the processor
method for processor
inform about the hardwar of the processor

a project plane
the imag data with the project plane
the imag data by a transaxi angle
forward project algorithm
everi axial angle
each y
data from an imag volum

a proport interv of time
transfer of a select signal i
time of each arithmet unit
third signal transfer circuit
third select circuit
third control inform hold
third arithmet unit
the switch of arithmet oper in each arithmet unit
the control inform hold circuit
each select circuit
control inform hold circuit

a provis
the perform monitor
the entir data
processor within a data
perform monitor relat signal between the variou perform monitor within the variou devic
perform analys
ani other devic
an entir data

a queue buffer
the valid data input
the self time logic i
the self time clock
the queue buffer
the overal instruct per cycl perform of the processor
the next pipelin stage
the function of each pipelin stage
the clock period in multipl time unit
synchron clock
self enabl clock
plural of time unit
pipelin processor design
more pipelin stage
function block
each pipelin stage of the processor

a queue stage
the queue stage
the pipelin advanc through the queue
the input of the next stage
the content of the queue
stall delay
queue between pipelin stage
earlier stage of the pipelin
a stall

a ram array
tripl port dynam ram
the transfer of all possibl combin of unit of adjac memori
the entir bandwidth of the port
the bitblt
pixel data within a graphic user interfac
memori control architectur for high speed transfer oper
block transfer of adjac unit of memori
bit block transfer
an align unit
a subsystem architectur for direct memori access of random access memori

a ram data memori
the viterbi memori
the ram data memori
select oper of the viterbi algorithm
devic with digit signal processor for the implement of a viterbi algorithm
a rom program memori
a ram viterbi memori

a ram with read output
word pair of word of each vector file
vector processor with data
vector file of programm regist
variou block of the vector file
thirti two element of 64-bit word
the vector file for either read operand
the vector file by the execut pipe for each instruct execut
the variou element of the segment
the file storag
storag for sixti four element of 36-bit word
storag for intermedi result vector
shadow storag
serial loop
secondari vector file
secondari file
scientif processor vector file organ
refer all n block in a pass
pair of element
n regist
n independ block
multipl program execut pipelin
independ execut pipelin in combin
each vector file
a vector file organ
a time slot manag mechan

a re order instruct cach
variabl length bundle
the set of instruct a a trace segment
the instruct into an instruct cach
the end of the bundle
the bundle in place
place of an instruct
nop
vliw instruct word length
variabl word length
the vliw instruct word length regist
the vliw instruct word length of the vliw instruct word length regist
the load of an initi program
the effect use of instruct memori
the case of normal instruct
object program for convent processor
long instruct word instruct processor with word length regist
instruct word length
instruct number regist
ani indic of the vliw instruct word length
an object program for a convent processor
a vliw instruct word length rewrit instruct
a vliw instruct word length regist
a variabl word length vliw instruct processor
no oper code
length bundle
instruct cach in bundle
a set of basic block of instruct in a logic order of execut
a re order unit

a read onli memori look up tabl
tripl shift
the central processor handle input/output oper
the central processor for data manipul
system flexibl
multiprocess comput
modular form around a common control
modular
control function for the variou modul
circuitri for instruct
bu orient

a read oper if the read oper
the same memori address
the same address
the problem of overwrit
separ read
read oper
overlap
memori access system with overwrit prevent
error writeback oper

a read out address of the buffer
the time share convolut
the result of addit from the adder
plural item of pixel data
period of time by delay devic
intermedi process result
each item of pixel data of a frame memori
convolut pictur
certainti
apparatu use coeffici matrix data
an amount equival
a time share basi with regard

a read phase
the problem of a read/writ clash
the phase of success instruct
the output of the execut unit
the match
the latter case
the execut unit a an operand
next phase at the end of each clock beat
each read
each clock beat

a real time video display
video imag inform
vehicl posit
transmiss by narrow band rf data
the video output of the sensor
the vehicl
the larg bandwidth reduct
the instantan posit
the frame data
the control station
the complement of the compress techniqu
standard data compress techniqu
remot drive system
narrow band data
human
frame rate
board inerti refer unit
bandwidth by a factor
attitud data
appropri control signal
a vehicl from a remot control station
a televis sensor
a remot control station

a rebound sorter a a merger
the rebound sorter
record storag element of a rebound sorter
record from separ group
pipelin record through the sorter
multipl record group rebound sorter
method for use with a sort acceler
input into the rebound sorter
differ group of record
consecut group of record

a reconfigur processor array
zone buffer with each side
the array memori
oper on data array
multizon array processor
i/o side
i/o bottleneck
array oper
an i/o side
a subsequ oper

a recurs accumul
transpos matric
thi circuit arrang
the aid of the recurs accumul
squar of sum
squar
row sum
maximum matrix element
matrix oper in signal process
matrix oper
differ of matric
differ
conjunct with neural network
column sum
absolut magnitud of sum
a systol array of multipli

a recurs mode
use with a digit signal process devic
the remov of the member
the member of a signal array
the electr configur of the digit signal process devic
the digit signal process devic
the control apparatu permit the digit signal process devic
the control apparatu control the locat of data
the applic of member of a signal array
signal array size
signal array overlap
signal array from the digit signal process devic
provis for automat accommod
plural of digit signal process unit
method for flexibl control of digit signal process devic
latenc in the signal member path
a signal array by a single digit signal process unit
a signal array
a seri of oper
a seri arrang
a sequenti mode

a redund binari accumul part
the supplementari term
the result of the redund binari multipl part
the result of the redund binari accumul part
result into the accumul result latch
product sum oper instruct
pair of partial product
mode of nonpipelin oper
high speed oper of multipl instruct
arithmet method
a valu of an accumul result latch
a supplementari term
a redund binary/binari convers part
a redund binari multipl part

a reentrant system manag mode mechan
remapp hardwar resourc
extern isochron subsystem
devic handler
a virtual subsystem architectur

a region approxim look up tabl
transcendent function approxim
the region approxim lookup
the region approxim
the placement of the radix point
the n bit approxim
the interpol processor
the interpol adder/subtractor processor
region lookup
rapid fix point arithmet calcul
lookup
interpol adder/subtractor
differ part of the input argument
approxim valu of transcendent function
an n bit result
an n bit argument

a region of memori
the permiss to fetch instruct
the memori type
the linear address of the instruct pointer
the ifu access an instruct translat look asid buffer
the correct branch
no previou branch mispredict
memori type
i/o side effect in a processor with specul instruct
demand for uncach memori
auxiliari branch predict mechan
an uncach memori locat
an instruct prefetch
actual execut
a result of a branch predict

a regist depend instruct
the execut of the regist depend instruct
branch on regist instruct

a regist file backup system
the first mean
first mean
a second mean

a regist file decod
the set of regist data
the set of operand refer from each instruct in the set
the set of operand refer
the regist file decod
set of scoreboard bit
set of scoreboard
scoreboard bit
resolut of data depend stall
regist from the set
each signal in the set of regist data
dynam locat
control of processor resourc
a set of regist data
a set of operand refer

a regist file in a first stage of the processor pipelin
the same regist file in differ stage of the comput pipelin
the first operand in a storag area
that storag area in a subsequ stage of the processor pipelin
more alu oper
memori access in a processor pipelin
differ operand
aspect of the invent
an instruct in a processor pipelin
an instruct in a comput pipelin
a second operand in a differ subsequ stage of the processor pipelin

a registr delay
use of excess azimuth bandwidth in radar echo signal
the radar antenna electr boresight for use
the mean energi in each separ look
the correct refer function for the product of high qualiti sar imag
single look imag line from an azimuth correl
single look imag line
real time multipl look synthet apertur radar processor for spacecraft applic
pipelin multipl look data
multipl look imag
an energi analyz
a spaceborn synthet apertur radar

a regular array of small carri save adder
two speed intern clock for oper
two node clock
system clock signal
point processor with intern free run clock

a regular array of small carri save adder cell
high speed absolut valu
circuitri for expon calcul
booth type multipl
binari multipl

a regular array of valu
tomograph x ray
these parallel circuit
the physic properti measur
surgic oper
surfac structur of the interior region of a solid bodi
surfac normal calcul
signal comparison
physic properti in the interior of the bodi
parallel circuit architectur
parallel circuit
parallel architectur permit gener of surfac view in real time
magnet reson
linear interpol
circuit path
arbitrari interior surfac of a three dimension bodi

a regular flow of data
these invent
the individu processor in the network
the form of a mesh
systol array network system
systol array apparatus for matrix comput
such array
some comput
regular commun path
mani basic matrix comput
data through the system
a varieti of other comput
a systol array system of inner product step processor

a replay
variabl latenc
reissue the instruct for execut
an instruct for execut
a replay devic within the instruct

a represent of a circuit
the sourc hdl
signal i/o access within the loop
loop from an hdl sourc code descript
infer a circuit
cycl level simul behavior

a request for the processor
the method of the present invent intercept instruct
pre determin resum instruct
power consumpt state
ani voltag level fluctuat in the processor

a requir
the portion of the instruct
reciproc oper
lookup tabl in each simd processor
iter process by an arithmet unit
instruct in an execut pipelin of a simd machin
geometri pipelin
a simd machin

a reserv
use by other oper
thi stream of oper
the stream of oper
the instruct in an out of order pipelin
the instruct cach memori lookup
the determin of execut readi
the data readi
the continu stream of oper
rotat
multipl instruct a a continu stream of oper
method for pipelin
instruct in a comput system
data readi oper
consecut pipestag
an instruct cach memori lookup

a reserv station with format convers logic
uniform extern format
the use of superscalar techniqu
the represent of operand data in uniform extern format
the implement of a superscalar comput
point reserv station from extern format
point reserv station convert operand format
non float point instruct becaus operand
non float point function unit
intern represent

a residu addit overflow detect processor
the result sum
the digit
the detect processor
residu number
residu addit overflow detect processor
conjunct with optic inform

a residu number system multipl overflow detect processor
y operand
these magnitud measur
optic technologi
operand x
multipl overflow
magnitud measur
invalid signal
detect of overflow in residu arithmet multipl
base represent of the product
base represent of the operand
an invalid
a valid

a respons from the xbio call in the storag
the storag for xbio request
the request xbio command
system secur measur
smm
replac of the xbio request by the xbio result
oper system
interfac for smm
interfac for extens bio
complet of an xbio call
an xbio request in a storag
an xbio request
an xbio call

a result data
the result data valu
the except if the except
the except data valu
the except data
the architectur state of the processor
specul out of order instruct execut
except in a processor
an except data
an asynchron event if the asynchron event
an asynchron event handler
an architectur state of the processor in the sequenti program order

a resynchron condit
the resynchron condit
the resynchron acknowledg
the reserv station of the function unit
resynchron of a superscalar processor
result entri at the head
redirect
order of dispatch
oper of a pipelin processor
function unit reserv station
buffer queue

a return address of an instruct for a subroutin
the valu of the current window pointer
the specul program counter valu
the multipl regist window
superscalar processor with multipl regist window
specul return address gener
regist window
multipl regist window pointer
instruct for execut by multipl execut unit
a watchpoint regist
a superscal processor
a specul program counter valu
a return predict tabl

a return predict unit
these tag
the content of return stack storag
return address predict system

a return stack buffer mechan
the specul return stack buffer
the second return stack buffer
the first return stack buffer
the content of the actual return stack buffer
the actual return stack buffer
separ return stack buffer
incorrect instruct
a specul return stack buffer

a revers feedback loop
triangular scalabl neural array processor
the output of a sigmoid gener
sigmoid gener
neuron
input multipli
a triangular scalabl neural array processor unit for use in a neural network

a risc processor
the processor interfac
the other for a memori interfac
the novel icu
the icu support
support of a combin of bu watch
programm cach memori
processor access time
processor access
ownership scheme
non risc architectur environ
low power requir
larger cach
high perform processor
hardwar control scheme
further featur
frequenc in excess of 25 megahertz
extens multiprocessor support hardwar
data cach with flexibl intern cach organ
cycl for the first access in a sequenc
cycl for burst mode
byte of cach
addit icu

a scalabl compound instruct
the overflow
result from execut of the first instruct
overflow in an interlock
overflow determin
overflow detect
onli valu input

a scalabl formatt element
univers compound document
transfer compound document data
the select intern format
the novel architectur concept
system implement
safeti
run time configur
reliabl with low cost
mind that a plural gener of these disc
mani potenti desktop
level of capabl
interoper arbitrari extern document format
circuit system design method
circuit system architectur for document instal

a scalar bu input
vector memori
vector distributor
vector coupler
unit of block data
the vector distributor
the scalar process unit
the oper of these circuit block
the block vector
scalar regist in the vector
perform becaus parallel vector instruct
parallel in the vector
output vector
normal data
input data a block vector
ident structur
each vector
each circuit block
a vector distributor
a vector coupler
a scalar process unit

a scheme
the type of activ
the independ control
more flexibl program execut
independ control
forward branch predict
differ environ
control over condit execut
condit execut of instruct for variou branch scenario
condit execut
condit branch execut in a data processor
bit programm access control field
backward branche
backward branch predict

a second control process
the odd phase of the clock
the data buse on the respect phase of the system clock
the critic pipelin resourc
the complex resourc alloc techniqu of the prior art
processor by clock phase for parallel execut of depend process
pipelin hazard
pipelin command
other schedul algorithm
no data depend sinc structur hazard
each process
critic pipelin resourc on the phase of the system clock
control process
an even phase of the system clock
alloc of resourc

a second devic
the second devic
the first devic
oper of the second devic
a signal i output from a first devic

a second intern code in a second cycl
unit output a first intern code in a first cycl
the second intern code in a third cycl
the multi function instruct into multipl intern code
the intern code from the instruct
the first intern code in the second cycl
multifunct instruct execut
multi function instruct execut

a second intern data
the vector arithmet unit
the same input operand
the intern ram
the input/output operand
the imaginari part of a complex operand
the auxiliari regist
partial result
intern ram
instruct within the arithmet execut unit
high comput throughput for digit signal process
differ real operand
differ of these input operand
comput result from the multipli
comput block
complex arithmet comput
arithmet unit in a vector signal processor
arithmet regist
an intern data buffer
an arithmet unit for a vector signal processor implement ieee standard 754 for float point arithmet
a set of auxiliari regist

a second level cach memori control
the subsystem
the local processor
the control tag array
the cach memori via the cach directori in the secondari cach control unit
secondari cach access by the main memori
secondari cach
second level cach control unit
memori bu cycl request
independ access by both buse
cpu bu traffic i
conjunct with a secondari random access cach memori
circuit unit
a second level cach memori subsystem

a second nmi request
time period after receipt of the first nmi request
the second nmi request
the first request
the first nmi request line
system on a second nmi request line
system on a first nmi request line
nmi request
differ sourc
circuit data

a second target
x2
the target of the posit
the target displac x
the radar devic
the radar beam from the direct
the radar beam
the individu case
the function valu
the function cours of these aerial function
the first measur axi
the aerial function
target displac
such direct characterist
phase monopuls radar devic
partial aerial for a first measur axi x
imaginari aerial function
amplitud single puls radar devic
amplitud

a secondari sonar measur system
the variou measur system
the secondari system
the inerti system
the inerti measur system
the digit record
the acceler orient inform
system within a pipelin
sensor for post ash
redund data
profil
product pipelin
primari acceler
oval
orient data
odomet
more pig carrier
inerti
featur of profil
displac of pipelin
displac of oil
digit record
detector
variou intens of a single color
these puls
the vessel
the signal part
the reflect of the puls on the seabottom
the record by separ color
the locat of a marin pipelin
the acoust wave
paravan
acoust puls
a vessel
a submarin puls transmitt
a strapdown inerti measur system

a select manner
use by the display
the intens level
the imag data on a select basi
the imag data in a random access memori
the imag data from the random access memori
imag memori
imag from imag data in the form of row
imag display system
imag data in the form of row
imag data in a display memori
imag data from the processor
form the random access memori
display memori
column of pixel with each pixel
an imag display system

a self time data pipelin
toggle
the pipelin stage in the self time data pipelin
the demand of the particular data pipelin
the combin logic i
self time data pipelin
logic element
data in an asynchron fashion through the use of readi
commod applic
combin logic i
asynchron stage

a separ far target cach the far target cach store limit
unit with a far target cach
the target cach output
the far target cach
segment limit inform
mode bit for far target
indirect from the target cach
ftc index
far target
entri in the far target cach
cof entri in the target cach
cof
an ftc index field

a separ regist file memori
user visibl inform
the regist file memori of the unit
the execut of differ instruct
success cycl of oper
place within a minimum of time
multipl unit regist file memori in success cycl
cycl of oper
certain input data
both regist file memori

a separ single modul of dynam random access memori
video inform from the camera
variabl length
the video codec
the redund of inform within a single frame
the pixel from spatial domain
the monitor
the compress of video inform
the commun channel bit rate
tempor decorrel of the interfram inform
spatial decorrel of the intrafram inform
pictur for both compress
pal compat camera
other video output devic
other video input sourc
intrafram
full duplex single clip video codec
frequenc domain
decompress procedur
chromin pixel block
block of eight by eight pixel
bit stream
a video input
a televis
a single chip video compression/decompress

a sequenc control of an instruct
the sequenc control
the pendenc of the execut of the particular instruct
the ipu in the readi state
the ipu in the cancel state
the ipu in a hold on old state
the ipu in a hold on new state
the hold on old state
the hold on new state
the execut result
the execut of an instruct
sequenc control of an instruct
more other function unit in the data
availabal
and/or the function unit
an error in the function unit

a sequenc of activ of the conductor for inform transfer
the conductor
more conductor
conductor asynchron signal
an inact state
an activ state in a sequenti manner
all conductor

a sequenc of branch target instruct in respons
the processor for execut
the instruct in sequenc after the branch if the branch
the determin of the exist of a branch instruct
the branch target instruct sequenc
primari processor
instruct in sequenc after the branch instruct
delay in instruct execut
condit that a branch
branch instruct in separ processor
ani circuit

a sequenc of instruct for parallel comput system execut
in memori preprocessor

a sequenc of instruct for superscalar execut by a central process unit
time of execut within a single clock cycl
the minimum processor clock period
the durat of the processor clock period
stage of the processor pipelin
resourc depend
execut at the begin of the next processor clock cycl
a single clock cycl of the processor clock

a sequenc of instruct from memori for execut
tow instruct fetcher
the point in the instruct sequenc
the effect branch signal i
execut of a condit effect branch instruct
dual instruct fetcher
branch system
branch instruct in a sequenc of instruct
anoth aspect
an effect branch signal i
a target locat

a sequenc of oper code with some code
thi refer unit
thi out of order execut
these latter oper
the refer pipelin
the output from the top-of the stack mechan
the former i
the code stream
the address coupl queue oper
pipelin level
order in a pipelin parallel processor
no stack input
input into the refer unit
concurr
ani number of read type oper
address for main memori
address coupl queue
a top of stack queue

a sequenti stream of input
thi input sequenc
the structur of the devic
smple
set of n input
sequenti sample within a set of n sample
proceng continu set of n sample
percent arithmet unit effici
novel arrang of shift regist
high arithmet unit effici
fft processor
each arithmet unit in the pipelin
an intern reorder of the data

a seri of calcul
sequenc the input operand
point processor by a seri
compound arithmet oper
arithmet oper on input operand

a seri of control element
the other control element
the fifo control chain
the data path
own path
greater freedom
fifo data path
data path circuit
control element of an adjac data path
control chain

a seri of dilat
the second frame of pixel data
the first frame a a function of the spatial relationship between these pair
the first frame
stereo project
similar featur in each frame
serial neighborhood
second frame
registr of multid landsat imageri
programm stage
point in the other frame
motion detect
mathemat distanc
landmark in each frame
imag point
imag correspond techniqu
imag correspond between multipl frame of imag data
exampl of particular use for the techniqu
eros sequenc
differ therebetween
a serial neighborhood

a seri of first result
the second result from the first calcul circuitri
the queue output the sequenc of second result
the first calcul circuitri
first calcul circuitri
fifo buffer for in order instruct complet
buffer output the seri of first result
a seri of second result

a serial diagnost link
those error
these stabl state condit
the system processor unit for error determin
the system clock of the cpu
the state condit
the point of synchron between error
the last stabl state condit
the execut of each instruct
the cpu system clock
synchron error
roll
process at the same time
preinstruct valu
load the cpu data
instruct sinc multipl instruct
execut of the current instruct
asynchron error
an impact upon the oper

a serial instruct
the pipelin of a vector processor
the memori access instruct among access instruct pipelin
the last stage of the plural of buffer if an instruct
the last stage of a pipelin
control system for vector processor with serial instruct for memori access for pipelin oper
an access instruct pipelin
an access instruct
a storag control unit

a set of address line in a memori
devic with multipl on chip memori buse

a set of entiti
volumin data base of larg commerci data repositori
the scope of design requir
the develop of data
mandatori relat violat in a relat databas
mandatori relat violat between entiti
certain relat

a set of instruct in a microprocessor pipelin
variou execut unit
the offset of an address
the chronolog age of each instruct within the set of instruct
the age bit
the address of an instruct stream
program counter age bit
instruct within a set of instruct
everi instruct

a set of n sample valu
the permut
the n sample valu
non median filter for signal
biolog signal input
biolog event
an odd posit integ

a set up core
the set up core
the l core processor
the f core processor
set up core
set up calcul for geometr primit
separ process unit
point processor for a three dimension graphic acceler
point processor for a 3-d graphic acceler
point core
point comput unit
perform over prior system
perform over prior art design
geometri primit data
comput for triangle

a shadow direct within the network
the unus rout compon
the shadow direct
the path bypass the unus rout compon
the path between node
the edg in the shadow direct
destin node
deadlock free rout around an unus rout compon in an n dimension network
deadlock free rout around an unus rout compon in a network rerout path between sourc
compon in the network between the unus rout compon
an unus rout compon
an edg of the network

a shift amount
the product of the significand
parallel with multipl of the significand of the operand
normalization/denorm shift amount
denorm

a short forward branch instruct
the short forward branch instruct
the processor pipelin a first group of instruct of the plural
the condit signal
the condit of the short forward branch instruct
the condit of the short forward branch
target instruct through pipelin
result in respons
result if branch
method step
intermedi instruct
each such instruct

a signal process system for a video camera
the use of a single neural network in place
the neural network implement gamma correct
the cost of the total system
signal processor in the video camera
neural network video imag processor
multipl nonlinear signal process function
effort
contrast compress
color correct
back propag
apertur correct
anoth exampl
a single neural network

a signal x
xi
n binari sample

a simple instruct
the path after a condit branch like instruct
program path after the test part of a condit branch
program path
path end with an uncondit branch
both program path

a simple microprogram
the success intermedi result for calcul of vector element
the output of each pipelin processor
the loop of the microprogram
the capac of the memori for microprogram
intermedi result of oper
each compon
an fifo memori

a single arithmet logic circuit
vector oper data
vector oper circuit
the execut circuit
parallel manner
graph a a program for a plural
control execut
an execut circuit on the pipelin

a single bit line pair
a single word line

a single chip integ unit
the local cach
the global cach
store of integ
point data for use by the array processor
local cach word
local cach with low latenc for use by the integ unit for load
integ store
integ data
coher between the local cach
array of data
an extern main memori
an armi processor store
an armi processor
a split level cach memori system for a data processor

a single chip superscalar microprocessor with graphic function unit
the special function circuit of orthogon rotat
page printer control

a single cycl in the event of an except condit
the variou execut unit
the origin instruct sequenc
recent valu of the set of architectur regist
recent valu of a set of architectur regist
data processor with futur file with parallel updat
a single sourc for operand

a single devic
control singal
all dram address

a single format instruct
valu for similar operand instruct
transfer instruct
the sequenc of regist number in the instruct
the second stage decod
the letter
the first stage decod process
the direct of transfer
the direct of data
stage instruct decod
stage decod
set of similar convent instruct
microprogram for execut
format instruct
an intermedi code

a single instruct activ
wide instruct
the issue of a single instruct
point perform in a vliw processor
point adder in combin for execut
other wide instruct
operand for usag
oper adder
multifunct execut unit
either unit
cooper for certain combin
concaten

a single instruct sequenc
the instruct in a sequenc
the content of the gener purpos regist a group delimit
multipl sequenc processor system
either taken branch instruct
contigu group of instruct
both method
an auxiliari pipelin processor

a single instrument entri in a memori array
the storag of instruct inform in the memori
the process id
the out of sequenc execut proceed
the occurr of a cach miss
the execut of instruct in an out of sequenc execut machin
other system condit
instrument
instruct identif number
iid until the memori array
iid

a single isdn line
the isdn interfac
multipl simultan call capabl
multipl call

a single mechan
type inform processor
the program data
the number of stage
program memori
program execut in the inform processor
program data
increas in program execut
both function
an operand data pair

a single pipelin by multipl instruct packet stream
the next machin cycl
the instruct flow comput
the individu unit
the first instruct packet of the second process
the first instruct packet of each process through the network
programm function unit
process in sequenc
place on the network
parallel execut of program in instruct flow form
mimd instruct flow comput architectur
full clock rate
each process control unit
each instruct packet
an interconnect network a self contain unit
all resourc of the comput
all commun among the unit
a uniqu comput architectur

a single precis float point arithmet oper
the total number of regist depend
the single precis instruct
the second microinstruct
the result in a phantom regist
the first microinstruct
the content of the phantom regist
single precis regist
single precis float point regist
single precis arithmet oper in system
second sourc regist
possibl regist depend
each microinstruct
doubl precis regist
doubl precis float point regist
an out of order processor

a single semiconductor
vector oper if a vector mode
vector execut control
the processor control
scalar pipelin replic for parallel vector element
scalar machin resourc
multipl parallel scalar execut unit pipelin

a single type of asic
raw data
processor architectur for front end electron
other data input port
method use
few clock cycl
each processor process data
dimension array of processor
data from a larg number of input
data for other processor of the plural
anoth processor in a single clock cycl
an effici microcod
an array of processor
a smaller number of output

a sink storag matrix for temporari storag of data element
the locat of sourc data element
the extract of low level concurr from sequenti instruct stream
the dynam execut state of the instruct in the queue
relat matrix
new techniqu
low level concurr from serial instruct stream
instruct execut from memori
depend between instruct in the queue
data independ of instruct
branch predict without state restor
an execut matrix
an execut independ calcul
an architectur for a central process unit

a six stage pipelin architectur with a cach memori
the processor function
similar circuit on the chip in order
other perform factor
on chip memori manag unit
ani peripher interfac input/output circuit

a six stage pipelin architectur with an instruct
the epu
specif function
slave processor in a comput system
high rate
busi signal interfac between master

a size
realtim applic
raster scan
output devic
multi dimension data
comput unit with 2logn processor

a size of the cach
the size of the cach
the sector
the cach into separ physic address sector
sector
multipl access circuitri
cach circuit with programm size

a small amount of storag
systol structur
simd systol array processor
memori in a more effici way
data between the multiport memori
array architectur

a small millicod address
address extens data

a smaller delay time
the temporari storag
exhibit larg delay
delay in data
an actual time
a temporari storag

a snoopabl request
the snoopabl request

a softwar command
the digit circuit
normal frequenc
normal clock
non destruct sampl of intern state
intern state
a test system
a test port

a sourc data valid flag
the specul sourc valid flag
the specul result data
the logic regist sourc
the immedi valid flag
state regist sourc data
state regist
sourc valid flag
sourc data in a processor
logic regist sourc
immedi valid flag
immedi sourc data in a processor
circuit issue instruct
an immedi operand for the instruct
an execut of the instruct
a specul sourc valid flag
a specul result data

a sourc of destin operand
the sourc operand
the address of the sourc operand
memori in respons
an execut unit in respons
address of the destin operand from the operand
a variabl number of potenti memori access conflict

a space
trace algorithm
the refer method
the output of the cellular imag processor
the non refer method
the non refer algorithm
the cellular imag processor
non refer algorithm
host imag processor
critic area of the circuit with sub pixel accuraci
circuit defect
cellular imag processor
both refer
an electron circuit
a topologi

a special inillicod instruct
the serial
the right prioriti
the pipelin control without redirect of the instruct stream
the millicod load with access test instruct
test access instruct
millicod load
load instruct except that access except code

a special instruct
the hardwar resourc
the complet of the oper initi instruct
stage of the oper
separ stage
complet of the except
ani hardwar resourc
an oper initi instruct

a specif bit of an exclus usabl regist by softwar
variat in the program
the reliabl of the branch histori
the exclus usabl regist
the branch predict mechan
predict mechan
initi branch histori
inactiv of the branch predict mechan
extern address
branch predict oper
applic of branch predict mechan
a specif valu into the exclus usabl regist
a specif valu

a specif pipelin multipli
usabl accumul
the same operand
that overlap
set of input operand while comput of the product
seri of product
processor cycl per partial term
partial section
output valu with set of input
output valu
differ output valu
arithmet devic
an intermedi pipelin regist
accumul of product term

a specif relat with a valu
third vector data
the second vector data
the oper of the oper unit
the first vector data
set of data signal
second vector data
result data signal
logic oper in a pipelin manner on vector data
group of data signal
a valu of each data

a specifi queue synchron counter
treatment of a variabl bit field operand type
the synchron method
the split of execut flow
the overlap
the operand in order
the operand context
the locat of operand data
the field queue
the autonom execut unit
synchron point
strict read
opportun
operand in queue
microprocessor chip
memori resid across the pipelin boundari
memori request oper among the autonom instruct
memori insert the request
instruct with variabl bit field operand
instruct execut flow
increas overlap
context depend execut flow
comput with operand context queue
an operand type
an operand context queue
addit access

a speech
the speech
the output of the speech
the other period
the input speech in a period
the input speech
the basi of the raw data of the speech
speech
raw data of a speech
listen
ear
convers unit a an output speech
convers unit
convers switch
convers process for the input speech
convers method
audio signal store
ani chang of the pitch of the input speech
an input speech
a speech without ani chang of the input speech in the other period

a speech synthesi applic
the lsp paramet
the element of the asic
the convent chip
the asic
the area of the lsp speech synthesi asic
serial shift structur
lsp speech synthesi devic
complement fix point serial pipelin arithmet oper
an lsp speech synthesi digit filter
an line spectrum pair

a split transact
use in a system
time of request
subsequ request for the same data
state transact on the address
signal block ciq
request tag queue
receipt of transact data
processor level cach chang
other devic and/or
more split transact
memori line transfer
mani such buse
grant
depend upon the request
data input/output buffer
data bu request transact
complet of an earlier request transact
coher input queue
bu system
arbitr bu carri
all devic
address bu arbitr
a transact until the transact
a subsequ requestor

a squash branch instruct
squash
execut of each instruct on the basi
electron comput
each branch instruct hold
an electron comput

a stall instruct
stall of a pipelin oper
execut of the stall instruct
condit on the basi of an output puls
condit on the basi of a stall
an operand part of the stall instruct

a standard pattern for water demand
variabl of pump
the pipelin network
the characterist
the actual water consumpt
standard demand pattern
optimum distribut of water
node of a network
fluid pressur in a pipelin network for optimum distribut of the fluid
everi node
demand pattern
control of the flow rate
consum
attribut of each area

a state vector
state vector for instruct group of a number
represent of sourc
multipl processor cycl
instruct dispatch decis
destin regist of instruct
data depend check on an instruct group

a statu predictor
the statu i
the pipelin cycl
the multiplexor
the earli gener of all shifter
the control for microinstruct
the appropri statu
the advers affect on the delay
superscalar machin by the addit status
statu predictor
shifter rotate/merg unit
processor implement
multiplexor design
critic path in processor design
all function unit statu

a statu word
the statu of the processor
the new overal statu i
the execut of a plural of instruct
the current overal statu of the processor
the current overal statu
processor after the complet of an execut of an instruct

a storag control apparatu onli vector element
vector regist in the vector processor
the storag control apparatu control oper
the pertin memori locat
the memori bank of the main storag
the memori bank conflict
the mask inform
the busi state
place in accord with the intrins system characterist
mask inform among the vector element

a store buffer in the processor
these transfer
point execut pipelin
integ to float point transfer
integ execut pipelin

a store on the extern bu hit a load buffer insid the memori subsystem of the processor
weakli order memori model
the specul state of the processor
the situat
the same load address in the load buffer of the processor
the risk
the processor snoop the system
the load oper in all subsequ oper
self consist order on a system wide basi
comput system with self consist order mechan

a store violat condit
the penalti of a pipelin recoveri process
the load/stor unit until the store instruct
the issue of instruct
the apparatu permit a load
store address
percent
the out-of order execut of load store instruct in a processor
the out of order execut of load/stor instruct
multipl instruct in a single processor cycl
apriori knowledg of load
a uniqu store barrier cach
the out of order execut of load/stor instruct in a processor
dispatchng

a subsequ memori read request
thi comparison no conflict bit
the write read conflict bit
the conflict bit
the address of the read request
separ conflict bit
i read conflict
first put
d read conflict
conflict bit
ani conflict bit
addit entri while a read request
a write read conflict bit

a subsequ microinstruct
the sensit of an oper of a microinstruct
the sensit
the remaind of the microinstruct
the remaind of a microinstruct if a branch by that microinstruct
full pipelin oper until such time a a branch condit

a substitut for the rest of the system
the test data
the rest of the system
the microcod of a bit slice microprocessor
system data
some test equip
program perform
oper program/hardwar bit confid
oper of the program a a built in test
onli power suppli
minim impact on the structur of the program
minim chang
little addit hardwar
difficulti in algorithm design
development test data
develop of the program
complet algorithm
bit slice microprocessor test system
avail microprocessor rom emul

a suitabl prioriti basi with respect
unit in a non multiplex asynchron manner
the use of uniqu handshak signal at each phase
success data transfer among data
phase oper
differ one of such unit
data transfer among a plural of differ unit of a data
data phase oper
asynchron oper
arbitr phase
address transfer phase

a sum stage
the invers of logic carri express
the dynam binari increment
the bit width of the increment
the binari increment
dynam binari increment
carri

a synchron stage
unit pipelin
the vliw
the plural unit
the plural thread of comput for execut in that unit
that execut of vliw
share regist file
regist file of other cluster through a cluster switch
plural thread of comput
oper from differ thread instruct word
cluster output
cluster of processor

a system manag mode mechan
virtual display subsystem in a comput
the burden
legaci hardwar
i/o space instruct into oper for high resolut raster graphic circuitri
backward compat
an environ

a systol processor
the error locat
parallel structur
matrix for detect
data transmiss code

a tabl i
word at a time in order that the instruct
the usual case instruct
the tip tabl i
the target address of transfer
the purpos of the predict of target address
the prefetch proceed
the prefetch mechan form instruct address
the pipelin depth
the past histori of those instruct
the frequenc of transfer
the correct of the tip tabl predict
the central execut pipelin
the actual execut of instruct by the central execut pipelin unit
tabl i
past histori of the execut of those instruct
no transfer
instruct per pipelin cycl
instruct in parallel with the execut
instruct for a central execut pipelin unit
instruct by a central execut pipelin unit of the central processor unit
inform in the tip
indirect predict
indirect instruct
execut of everi instruct
execut by the central execut pipelin unit
doubl word of instruct
central processor unit for a gener purpos digit data

a tag cell
track of the precis of the individu operand
the precis of the operand
the precis of an operand in a multiprecis float point processor
the operand in the alu
special softwar
precis tag
oper operand

a tag store
the use of self modify code
the respect cach
the cach on certain condit
the alpu
most condit
main memori locat
ipu
either cach
each cach
dual cach for independ prefetch
digit comput processor system
data in the operand cach
an arithmet logic process unit
alpu

a target branch address
the target branch address after the instruct
the convent branch address calcul for an advanc control processor
the condit of the branch instruct
system for branch instruct

a target program instruct loop
time revers schedul of a data depend graph
time revers instruct
the process of modulo schedul loop in the target program code
the data depend graph of the target program instruct loop in order
schedul of the loop instruct
modulo constraint
all modulo constraint

a techniqu for restor
write back oper
write back inform
write back i
the second latch
the requir of addit clock cycl
the output pin upon the begin of the next bu cycl
the output pin
the output pad logic circuit within the microprocessor
the first latch
second latch
reload the output latch
output inform at the same time
oper within the microprocessor
each output pad logic circuit
an output pad logic circuit

a test function
these individu stage
the sever pipelin stage
the input unit
the individu pipelin stage

a textur color valu
textur filter

a third cycl
point oper in a next success cycl
point circuit
point arithmet oper on an operand
point arithmet oper on a set of operand in a first cycl
cycl data

a three to one adder
the three to one adder
the implement the delay
the embodi
the design complex of implement altern
the critic path delay of each embodi
scism alu
reduct in delay
minimum delay without a prohibit increas in hardwar
high perform interlock
high perform implement for an interlock
avail bookset
an equival number of stage

a threee dimension volum
the imag volum at variou posit

a time across the memori
word of data
word at a time
word align
the slower extern bu
the minimum number of word
the extern bu from an extern devic
the entir block of data
the end of a block transfer
the data onto the memori
the bu control in order
portion of the block
extern devic from the memori
burst transfer
an extern bu control
addit cycl

a time of the oper execut
the function unit in respons
signal i output
self time processor with dynam clock gener
self time process

a total latenc clock count valu
the total qualifi cycl count valu into the total latenc clock valu
the total qualifi cycl count valu from the first counter
the total latenc clock valu from the second counter
the sample period by the number
the averag number of clock of latenc
the averag latenc
split transact request
split bu transact within a comput system
split bu transact
p6
logic divid
divid logic i
averag number
an intel pentium pro
a total qualifi cycl count valu

a trap upon modif of the pipelin
unnecessari save
trap gener capabl
the save of pipelin
overal system perform
certain trap

a two port branch predict buffer
variou stage
use in a pipelin processor
the same clock puls a registr of anoth branch address
the branch predict devic of thi invent
simultan oper of the registr
simultan access
retriev process
memori access stage
branch predict devic

a two stage cach access pipelin
those result
the processor within the same processor cycl
the processor cycl time
the novel method
tag modif
suffici time for the cach control
single cycl cach
polici
embellish
effici cach
an effici cach

a two wire interfac arrangeda a pipelin
ovef the single two wire interfac

a ubit
xbit
sub system portion of the comput graphic adapt
stream of command
more statu bit
method for graphic
execut of variou logic function
each raster of a multi raster render
decis variabl hardwar
data manipul within a graphic
an xbit
an rbit
a zbit

a uniform number of cycl slip
time relat hardwar problem
thi cycl slip data
the rate of execut
the overal rate of the instruct processor
the execut rate of slower peripher devic
the execut rate of an instruct processor on an instruct by instruct basi in a data
temporari fixe
system test
rate control data
programm processor execut rate control
number of execut cycl
each instruct type
data for each instruct type in the instruct

a uniqu bu protocol in conjunct
data valid control signal for high perform data

a variabl durat clock circuit
worst case data transfer
travel
the variou process element
the instruct of the program
the convent
the clock waveform within strict rule
the clock waveform
suffici time in everi clock cycl for worst case data
skew sensit activ
short durat for short data transfer
remot process element
recogniz edg
programm variabl cycl clock circuit for skew toler array processor architectur
programm durat control
operand suppli
no time
loss of sharp
durat
data transfer in an array processor of myriad process element

a varianc in a search effort along differ subtree of a backtrack search tree
time along the differ subtree
the subtree
the search tree
the differ subtree of the search tree
processor in parallel along the differ subtree of the search tree
processor alloc method
multiprocessor execut of a constraint satisfact search
differ subtree of the search tree
an instanc of a constraint satisfact problem
an appropri number of processor
an amount of search effort
amount of search effort
a varianc in search

a varieti of neural network
type network
the invent circuit
neuron with a varieti of differ activ function
dimension systol array architectur for neural network
dimension systol array
data flow in the systol array

a varieti of sourc devic
video camera
two dimension textur map
two dimension textur imag
two dimension scanner
three dimension data
stamp
specif form for certain effect
object in the display
figur
dynam display
comput graphic for anim by time sequenc textur

a vector comput
white address of the memori
the vector data from memori
the vector comput
the read address from memori
stage of a pipelin
recurs instruct
read/writ control
ani stage of the pipelin
an oper result in memori
address with a read address

a vector element number
normal process of the instruct
an instruct window

a vliw architectur
parallel process power
an arithmet oper unit

a vlsi graphic
vlsi graphic
system of fuch u
pixel memori cell
pat

a wait command
sequenc control circuit for a comput
function in respons
data bit in the microinstruct word
command in a digit comput

a wave digit filter
wave digit filter
the implement
the construct of wave digit filter
strategi
potenti hardwar limit of wave digit filter
port adaptor
higher speed
high frequenc digit signal
delay into the feedback loop

a wide varieti of optic comput
two dimension modul
the programm process of the optic data beam
the plural of modul
the optic data processor
the optic data beam
the focusless transfer of the optic data beam between the modul
programm multistag lensless optic data
lens
an optic data beam
an optic data

a word line
word line input
third switche
third memori cell
the word line input
the second sens amplifier/writ driver
the second block
the first sens amplifier/writ driver
the first block
the bit line inputs/output
second switche
second sens amplifi
second memori cell
second block of memori cell
second block
row of memori cell
memori cell
fourth switche
fourth memori cell in a row of the cach memori
fourth memori cell
each memori cell
bit line switch array for electron comput memori
bit line input/output
an address decod

absolut valu bit circuit
the carri save adder
full bit level pipelin capabl
anoth mode of oper
an array of bit level carri save adder with each carri save bit adder

access by a plural of instruct stream
each instruct stream
arbitr time slot

access memori
the use of the random access memori
the effect of ani time delay in overal memori access throughput
servic mode adapt for each individu port
own resid
multipl commun port
main system memori
logic control architectur
inher time delay in a manner
both dma access
arbitr dma/interrupt control
access mode of servic

access of the interfac circuit
the flow of data between the processor
the exchang of data in the form of packet
the data storag devic between the processor
the data storag devic
the bu interfac
signal from the interfac control devic
identif signal
bu i
an interfac control devic exchang
an access control devic

accord with the comput program
time for m
the m physic buffer locat
buffer locat
buffer for instruct
an extern memori via a system bu

accumul that work with pipe stage
the substructur
the result of the stage
substructur
multipl accumul
each accumul for each calcul
calcul at a time

action in a stage
the action of a stage without possibl of interfer form adjac stage
problem
the output request event from the input request event
the output request event
the latch time of the data
the intern signal of the pipelin
the delay from input request event
the correct synchron signal for synchron sourc
the correct asynchron signal for asynchron sourc
signal chain
request event
output request
output circuit
load signal buffer
load signal
everi stage
destin devic
delay between stage
delay between adjac pipelin stage
asynchron pipelin
an asynchron pipelin
neighbor
mutual exclus element
input event
control circuit of mutual exclus element
certain system
an adjac stage
an activ stage

action within the data path element
transfer of control
the routin
data path element

actual segment bit
the operand size
the correct process
the address size for memori refer
the actual segment bit
self modify code in a microprocessor
segment bit
each instruct address in the pipelin
an instruct verif method

addit circuitri
the regist file locat
the further inform
queue after an instruct

addit flexibl
these type
the third phase in the pipelin
the same time that the branch
the present invent permit effici accomplish of signal process task
the instruct address regist
the end of phase
the content of the data
the content of a common data
the alu oper output
that result from the execut of such instruct
such sequenc
separ
oper for instruct
interrupt protect
instruct of the processor
indirect branch
hot
data bu bit
branch latenc

address concaten
operand access control regist

address from the system
data from the processor core

address gener by execute/stop instruct
the address in advanc in the address gener
the address gener unit
stop of address gener
onli execut
input digit signal
design of the execut

address gener interlock situat
the input instruct stream
resolut of condit branch instruct
fewer condit branche for the pipelin processor
execut delay in the pipelin processor
branch stream pre execut processor for pre execut condit branch instruct
an instruct stream for input
an approach

address line in a memori
auxiliari arithmet logic unit

address port
plural of memori
plural of arithmet logic unit

address prepar unit
the other execut unit
the avail instruct level parallel
the addit of a supplement integ execut unit
the add/mov unit
small increment cost
physic address gener for memori operand refer
instruct level parallel
execut unit of a high perform processor
control transfer
better use
amu
supplement integ execut unit
primari integ execut unit
move
pipelin throughput via parallel out of order execut
move in a supplement integ execut unit

address valu
the system effici
the new function
the condit regist control recalcul
the condit regist
the code by the compil
tabl address valu
tabl address regist
tabl address calcul until the valu
tabl address calcul
tabl access
specif routin
sourc code
postpon
modul boundari
local function
librari execut code
idl cycl
extern function
current regist

advanc of execut
the instruct in the sequenc

all arithmet except
the sourc of the except
the sequenti program instruct
the same context environ
the identif of an arithmet except condit
the execut of the drain instruct
the drain instruct of the present invent in the program instruct sequenc
the drain instruct
no arithmet except
method for synchron of arithmet except in central process unit
high degree of probabl
an instruct sequenc after an instruct
an arithmet except

all inform about an instruct
the applic of thi method
storag element in the processor
set of vertic
second set of vertic
oper in the processor
inform about the processor
hardwar of the processor
code gener phase
code for the processor
code for programm processor
code for a programm processor
bipartit graph

all such further execut of plural processor upon the detect of an except
time the other processor
the time further execut of the instruct
the inhibit of the except
the except caus
select execut cycl count latenc
re execut instruct
occurr at the time the except
no op instruct
integ processor
instruct word of a program
instruct pipelin depth
further instruct execut
further execut of the except
further execut
execut befor execut of the except
detect of an except

all task of the pipelin
the extern procedur
task of the pipelin
header data
emul
the pipelin of microprocessor
that memori access latenc
system program code
synchron between a processor pipelin
subsystem pipelin
sever execut phase
pipelin of microprocessor
instruct memori
function execut unit
fetch/decod unit
extran oper
emul unit
data memori 22
circuit 42 with microprocessor
circuit 42
an extern test system
an emul unit
data from the pipelin
an extern procedur

all younger instruct from the fifo memori in respons
trap in a superscalar processor
the appropri trap handler address
stage for execut
softwar trap
program instruct in a superscalar processor
instruct from the fifo memori in accord with rel age of instruct
identif of a trap in an instruct
hardwar trap
consecut instruct from an instruct cach
an instruct fifo memori

altern
the pariti error
the instruct processor in a data
the error inject system
programm oper mode
programm indic
pariti error into instruct after the instruct
pariti error inject system for an instruct processor
error inject
each programm indic
comprehens test of error detect
comprehens test

an 8 byte block of instruct byte
the target instruct address
the low prefetch address by increment
the low prefetch address
the higher order
the high prefetch address
the bit posit n
sourc of prefetch address
prefetch size
no carri ripple
low prefetch address
high prefetch address in a single clock
an exemplari embodi each prefetch request
an 8-bit valu

an 8-bit adder circuit
the sign bit of the 8-bit operand control the mode of oper of the increment/decr network
the least signific byte of the result
the least signific byte
the increment/decr network
the adder circuit
the 8-bit operand
signific byte of the result
signific byte
delay time
carri anticip circuit
an increment/decr network
an 8-bit operand

an amount of time
thi output
the output of the second data
the logic transit
self time featur
product of the detect
low power transit detect
circuit that an output of a second data
an occurr of a logic transit at an input of the second data

an apparatu for the transform of pictur inform
the scan line
the pictur from a display file memori
the field of raster scan comput graphic
the display raster into a form
scan convers
preced in the display of the scan line
piec of inform in a scan line buffer memori
piec of inform
line segment
dimension planar coordin system

an apparatu i
valu of result
valu of operand of instruct in a processor pipelin of a system
result valu in a processor pipelin

an application/driv program
virtual the appropri behavior
virtual subsystem architectur
virtual process
the virtual process
the motherboard
the index/data pair
the execut of an i/o read oper without invoc of an smi
phantom read regist
oper avoid engag of the system manag mode a fulfil of the virtual process
multipl index/data
logic statu inform in respons
index valu
index of index/data
index for use in the virtual process
engag of the system manag mode a fulfil for the virtual process
chipset logic circuitri
application/driv softwar retriev
an i/o read oper

an arbitrari number of the instruct
pipelin identif tag
parallel by differ pipelin

an arithmet system
the arithmet i n cycl befor complet of the execut
pipelin structur arithmet mean
n arithmet in pipelin for n instruct
initi of arithmet oper for a new instruct in the arithmet unit
differ arithmet cycl
arithmet system
arithmet oper for the new instruct
arithmet oper for instruct
an arithmet unit of a pipelin structur

an array prefetch system
variat in latenc of memori read oper
the array prefetch system
request for subsequ iter
loop program
execut until a read access
complet of a data access
array prefetch

an earlier instruct
thi result in a deadlock
the rest of the pipelin
the pipelin if operand
the operand for the later instruct
the memori request for the operand becaus the pipelin
the later instruct
the earlier instruct
the case of a deadlock
separ microinstruct pipelin for the execut unit
digit cpu with deadlock resolut

an effect subtract
the magnitud ed of the differ between the expon of the operand
point addit unit
point addit method
normal of the result

an end of the process in block unit
the input/output section
start
end signal block start
data via the memori section in block unit between the input/output section
an input/output section

an energi
word sequenc
voic respons system
the entir word sequenc
termin of speech
speech recognit technologi
matur
like speech recognit result
earli end of speech detect
continu speech recognit
avail speech recognit result

an execut complet report of an instruct
the respect resourc with data item
instruct in resourc befor complet
execut start control
execut of the consecut instruct in the resourc
execut control unit
an instruct hold unit

an execut queue
the identif tag
an identif tag

an execut sequenc
the schedul issue oper in the order
the last oper for an instruct
the global field
schedul execut
processor that decod a multi cycl instruct
operand field
more entri
an instruct decod in a processor decod an instruct

an execut write pipelin stage
the execut write stage
the execut write pipelin stage
the destin of an instruct
signal process system
short pipelin
encod a particular instruct
embodi of a digit signal processor
each embodi

an extens bit
use extens bit
non preliminari instruct in order
larg data width
instruct in a data
extens bit

an fft
r result from the fft
r complex number data
comput in the memori
complex number data

an fifo input memori
the input buse
protocol unit
free space
devic among a multipl
data exchang of data
command modul command
command modul
an fifo output

an imag analyz system
the stage wherea local command
programm neighborhood transform stage
imag analyz with common data/instruct
global type
command signal

an imag data processor
void
variou subprocessor
spot
size detect
pixel normal
imag data processor
background suppress

an immedi valu
the sourc operand of the instruct
the destin operand of the instruct
step code
an operand of the instruct
an instruct into a plural

an independ condit regist
test condit valu
other condit
multipl field
multipl condit code field
instruct content free access
execut code for the comput system
each field
differ field
condit valu

an individu basi
the memori cycl
kbyte block of memori
concurr memori control
chang of the memori devic

an initi oper model
processor oper model
gener method
automat instruct

an instruct address in the execut complet step in the execut stage
these inform
the time point
multistag store buffer
data in the store buffer
area of a memori

an instruct cach element
these dma
the instruct from the first instruct sourc
the instruct cach element
the first processor in the same manner
the first process element in the same manner
the first instruct sourc
the ceu
program step
instruct into processor instruct stream in order
instruct from the first instruct sourc
instruct from a first instruct sourc
input/output
digit valu
digit multiprocessor method

an instruct of an address
the content of the branch histori
the content of branch histori
the branch destin address of the branch instruct until the instruct
prefetch address
instruct in pipelin processor
histori of the result of execut of branch instruct

an integ pipelin
the pipelin align between a pipelin
tempor
risc instruct onli use regist operand
rapid
point pipelin near the end of the integ pipelin
point pipelin for execut
point pipelin at the begin of the integ pipelin
pipelin coordin
muxe
memori operand
facil of the integ pipelin
complex cisc fetch oper instruct
both cisc
an integ pipelin for emul of a load oper architectur on a load/stor processor

an integ power of 2
two dimension dct algorithm
the two dimension case
the split radix discret cosin
the split radix dct method
the embodi of the invent
th order invers dct
th order dct
split radix discret cosin
oper in pipelin architectur
differ input size under softwar control
an nth order dct
an n length real number discret cosin

an intellig disk
parallel operand
error correct under program control
error correct control
ecc/edc control
disk
correct capabl

an interlock of an instruct pipelin
the cach manag logic i
storag unit manag work
selector control
instruct for select by the storag unit
cycl of the interlock
cach storag unit util
cach access throughput

an interpret
thi pipelin
thi file
the content of thi file
the content of the initi script file
languag
form in a script file
comput softwar

an interpret type digit data
program protect

an interrupt of the program
the sequenti count of the set of data
the conceptu order of appear in the program of the instruct
program at the appropri point
execut statu order

an invoc architectur
processor resolv instruct
other of the processor
invoc architectur
instruct at the invoc
homogen processor
each homogen processor
concurr process resolut

an irrevoc action
unit in due cours
unit control logic
the correct/incorrect indic
opportunist use of pre correct data
incorrect data
gate the action
error statu i
error correct hardwar
data from the output of error correct hardwar

an on chip dna control with on chip memori
transfer control
the use of system
the uncondit start
the synchron mode
the statu of the dma oper
the dma oper in the sourc
the dma after the current read
the control regist
termin for the microcomput
synchron bit
start code
purpos of dma
on chip port for access
dma synchron
destin mode
complet of a data word

an oper code compress
the ram interfac with branch logic mean
progress in the system
oper code a an input
opcod
the use of numer control option
the execut unit upon detect
problemat instruct
microprocessor oper
instruct match register/execut control regist
instruct depend execut control on a microprocessor devic
each problemat instruct
control of the microprocessor
embed
each instruct into a new oper code of lesser bit
branch data in a branch predict ram after each branch
bit into the new oper code

an oper mode regist
the oper mode regist
store mode data
invalid oper mode
indetermin oper if invalid mode data
certain oper

the use of ani number of avail parallel process unit
the benefit of parallel process
sequenti manner
optim signal process
number of avail processor
manag hardwar complex
lattic coeffici in an optim manner
autocorrel coeffici

an optim parametr signal processor
optim parametr signal processor with lattic basic cell
hardwar complex

an output the instruct
single chip pipelin data processor
operand cach memori for parallel oper of instruct control
instruct read

an overflow detector
the sourc data
the result data by the largest overflow bit number
the largest overflow bit number
point mechan for a fast fourier transform processor
point mechan
largest overflow bit number

and/or multipl function unit
those instruct in an order
the time that the instruct
the sequenti order of instruct
the program flow
the perman state of the machin
that sequenti order
sequenti flow inform
sequenti coher instruct
sequenti coher except
program after the except
overwrit the destin
instruct in that flow
dynam schedul of instruct
complet inform about the program execut
coher data in a processor
and/or sequenti coher except

ani bi tonal imag
the resolut of an imag output devic
the resolut mismatch of the output devic
scaler gate array
method of the present invent
laser printer
fax machin
document resolut
document archiv applic
crt display

ani buffer
the present number
the pictur number
present number at ani time
pictur number
buffer manag

ani practic use
the success stage of the pipelin
the same logic circuitri
power down system
each stage of a pipelin

ani scale
the same compon
the interconnect network
that messag content in the interconnect network
switche with fifo queue
separ rout network for input
rout n input
network modul
memori interconnect network
m switche
m output

anoth dma bu master devic so that inform
the slave dma
the master dma
the dma devic
the bandwidth requir of the common bu
more dma devic
dma transfer across common buse
dma devic
common buse

anoth vector regist
vector shift function unit

antenna
locat transmitt

apart building
use with a hot water
the temperatur
similar multi unit structur
hotel
hot water heater control

applic of instruct
maximum effici in oper
further interleav instruct
effici operand

architectur design of processor
the specif instruct
the processor for execut in a manner
the instruct store the instruct
the instruct storag of a single machin
the fetch from address in the instruct store
plural incompat instruct format
method of oper permit
instruct in differ format
incompat plural format process instruct for dissimilar processor
differ machin type
both ordinari processor architectur
area of the instruct store

architectur for the real time comput
transposit
sine
put rate of n clock cycl
orthogon
n success serial input with parallel output data
local interconnect in both data
hartley
continu input data stream

architectur state regist
the write of an architectur state chang valu
the instruct processor with enough time
the architectur state chang
the appropri architectur state regist
period of time

array logic i
the burst mode
data from a memori
burst oper into memori

asynchron host processor interfac
versatil protocol adapt
use in primari rate isdn
time swap
time channel
the network interfac
tdm digit link
state in these pipelin in synchron with channel time slot at the network interfac
servic digit
ram memori
protocol data
plural function
oper in the synchron section pipelin
multipl channel of voic
mode of oper of these queue
memori queue
logic in the synchron section form
full duplex data throughput
extern processor
extern process system
effect on chip size
each time slot
critic time depend between consecut pipelin stage
control with synchron link interfac
commun data
channel statu inform
asynchron special purpos logic section in the devic

atyp instruct sequenc
typic instruct sequenc
the use of a memori refer
the pipe stage
the normal microcod flow
synchron pipelin except recoveri
pipelin except
no addit logic for condit write of state
grace except
command latch
caus except

autocorrel
optim parametr signal processor for least squar finit impuls respons
filter coeffici of the system in an optim manner
cross correl coeffici of a system under studi

basic type of circuit
shuffle
fifth stage
data compon
comput stage
coeffici from a plural

binari bit
the subtrahend
the smaller number
the result of the addit
the origin regist
the number of guard bit
the complement
that time
round off accuraci
point processor architectur
number of guard bit

bit 3
the second compar
the instruct prefetch phase of oper
the first compar
the debug address regist
the 32-bit prefetch instruct address against the code breakpoint
the 32-bit prefetch instruct address
the 29
such comparison result in a posit match
softwar debug oper
phase of oper
digit compar
debug address regist
comparison of the same prefetch instruct address
code breakpoint decod
code breakpoint

both way on each clock cycl
variabl load
store interfac instruct
select memori address preincrement
multipl coprocessor
interfac instruct
function call
compil generat softwar type function call

branch delay slot
the delay slot
the branch in execut order
the branch delay slot instruct
multipl instruct execut pipelin
branch instruct in a comput processor
branch delay slot instruct

branch direct
variou separ structur
the cost perform trade off
target instruct aspect of branche shift
single structur branch predict cach
signific portion of hardwar cost
dynam branch predict for target address
design complex

branch evalu
method for watchpoint

branch instruct from a branch predict
the branch predict inform

branch predict in a manner
specul state
specul chang of state
method with branch predict
instruct execut apparatu i
instruct befor the correct of the predict

branch predict state of branch histori bit
the strength of the predict
the pipelin resourc
the pipelin if the branch
the infrequ resolut
the branch target instruct into the pipelin
power the data processor
more pipelin resourc
disrupt
disabl a branch target instruct cach
disabl
differ power mode
branch target instruct

branch target address for use
system with reserv instruct execut

bu agent
transact request
transact across a system
that track
snoop in respons
processor order
long latenc transact

buffer storag equip
thi storag control
request with prioriti

built in pipelin stage
the widest possibl data
the cach by the processor
the burst mode data access
the addit perform optim techniqu
system respons time
system bu capac
request everi machin cycl
reduct in the system respons time
processor request in each machin cycl
maximum parallel
logic in the cach
data input/output circuitri
cach of the present invent
cach access oper
burst mode data access

bypass
use a putaway
the result of each multiply/divid oper on a bypass
the output from the adder
the input of an adder
point arithmet unit with a putaway
control of the accumul
control by the central decod

byte equal
these millicod instruct
special millicod instruct
replic byte
portion of a millicod
inner
equal
byte instruct

carry
multipli array sum
fast sign

circuit area than translat tabl type virtual memori system
those function
the pipelin data
such address
similar devic in virtual memori system
real address in main memori
main memori in the same amount of time

cisc instruct into a nano instruct bucket for execut by a risc comput
method for extract

clock cycl of the branch instruct
the state of the system
the pipelin architectur
the instruct at the address
pipelin delay
execut without delay
execut of branch instruct
execut at the begin of the next clock cycl

column address strobe
one cycl dram page mode access at high oper frequenc
dram access system

column independ section
the system frequenc
memori section
mask oper
data in a synchron memori
data for each memori section

column selector xsel of selector circuit
written/read
the input/output termin of memori array
the demand on high speed oper of mpeg
row selector
memori array control
memori array
input/output buffer
imag memori unit
imag block
high speed write/read oper of imag inform in unit of block
half pel oper circuit 24
each memori array mai

compens code
the origin loop count
the optimum locat
the latenc of memori refer
the elimin of extra branche from the loop
the elimin of condit branche
the amount of loop expans
scalar replac
other optim
modern risc architectur
loop with earli exit
intellig loop

compil of the instruct
the group of instruct
the appropri group of instruct
superscalar comput architectur
group of individu instruct
group identif tag

complet of branch
complet of the branch instruct

complet of the entir micro instruct sequenc
the restor logic
restor logic i
regist chang
particular regist
particular micro instruct sequenc
execut of a micro instruct sequenc
execut of a micro instruct
content of the particular regist

comput instrucrion by circuit
differ latenc

comput system with power manag featur
the intern clock of a microprocessor

comput with dynam instruct
valid of operand valu in regist
memori for the instruct
instruct by an invalid system
index instruct result
depend for operand between instruct

concurr processor access request
virtual sram perform

configur by way of extern arbitr
the output line of anoth such processor
the output data
the neutral valu
such output stack
parallel connect with the output data line of other such processor
parallel and/or
output data line
neutral valu
interconnect with other like processor
control over sever such processor

constant use
the step load of ani electron system
structur of power
step load
more function unit
maximum power

constel point in qam/tcm modem applic
tcm modem algorithm
sequenc of vector dsp code instruct
parallel oper cpu core

control flow instruct in a comput system
the control flow instruct
the arithmet instruct
control flow instruct in a control flow pipelin in parallel with arithmet instruct

control return
servic routin i
pipelin of the processor

control signal from a single chip
dram address

control store for each possibl instruct in a group
more adjac instruct
microcod sequenc for each instruct of a group of instruct
microcod in a scalabl compound instruct
microcod gener for a scalabl compound instruct
inform into a single microinstruct sequenc
independ microcod

convent float point multipli
use of idl stage
squar root take
point multipl
oper in a float point numer processor
minim addit circuitri
iter calcul

convers of intern processor regist command
i/o space address

copi of the reduc instruct into the schedul
the number of certain overhead instruct in modulo
the execut of modulo schedul loop
the balanc of the instruct with normal modulo
reduc overhead instruct
overhead instruct

coprocessor calcul instruct
the coprocessor instruct
the coprocessor calcul instruct
the calcul result on the second bu
microprocessor system
data from the main processor
data from the coprocessor
coprocessor instruct
coprocessor calcul result

coprocessor interfac
the bi direct bu i

correct
return address stack

cosin
the transmiss of certain digit valu
the number of elementari comput devic
the minimum number
the elementari comput devic in seri in an order
the arriv of the valu
such comput devic
sever time for the calcul
oper of the multipl
oper of the addit
monodimension cosin
embodi of a devic
elementari comput devic
each step of the success of calcul
each elementari comput devic
delay devic

cost effect digit video decompress
the total number of instruct cycl
the invers quantiz
the idct
motion compens function for an mpeg decod
motion compens function
logic oper in a superscalar microprocessor
digit video decompress

coverag in multi process comput environ
the initi of error infect one of such process
specif one
error recoveri activ

cpu architectur
time of execut within single clock cycl

cpu pipelin
the nonbranch sequenti instruct stream
stage between an instruct
nonbranch sequenti instruct

crossbar switch with select pipelin delay
parallel comput architectur

current room in the first tier buffer
tier system
tier prefetch buffer structur
those valid instruct byte in the second tier buffer
those instruct byte from memori
the second tier buffer
the instruct cach memori from the extern memori
the first tier buffer
space in the first level buffer
second prefetch buffer
room in the first tier buffer
method with bypass

data after a system clock
the use of dynam compon in the architectur
the static compon
the second circuitri
the first circuitri
the dynam compon
such devic a intermedi pipelin regist
static compon
size consider
second process circuitri
processor execut in pipelin
first process circuitri
execut after the system clock
dynam logic
dynam compon

databas sort
multipl memori array

design of operand
transferr stackpoint in a data processor
the transfer of instruct through the stage of pipelin
result of address calcul
execut of a plural instruct

destin of operand for the instruct
the logic regist
the instruct refer
set of logic regist
processor with regist
multipl size regist
multipl address size a sourc
more instruct pipelin
excess of the number

detect of leak in pipelin
locat of a leak in an underground pipe

differenti equat by asynchron commun system
the respect element processor
the oper of the other element processor
the oper of individu element processor
intercommun of data between adjac element processor

digit convers system
these state estim
the spectrum of the modul output
the perform of sigma delta analog
the output of the decim
the nois floor of the signal band
the modul with an observ circuit
the digit domain
state valu
sigma delta modul
minor modif
estim of the modul

digit process unit
oper of a parallel process array

digit signal processor system
instruct into intern processor memori

digit signal processor with condit branch decis unit
storag of condit branch decis result

dispatch the process
the sum of pipelin stage
the program counter for the process
the next instruct in the process
process between processor
other processor for execut of the next instruct in the process
multipl pipelin stage
more process than the sum of pipelin stage for all processor
mani process
execut of an instruct for a particular process

duplex
standbi state

duti cycl of perform control puls
target perform valu
oper of processor

each independ stack
the top
the independ stack
the destin operand of the instruct onto the independ stack
stack for a microprocessor
occurr of an except
multipl independ stack
map stack
independ stack

each stage of the execut pipelin
the index tag
the cach line number in the instruct cach
self modify variabl length instruct
index tag

effici of program
vector oper function
multi processor construct
memori access in short time period
instruct for an exclus control by combin of a few simple instruct
high oper perform

end such method
method for a time out checkpoint

eprom/otp memori cell
the time of manufactur
separ metal layer
point operaton throughput control
oper of the main processor
oper of a main processor
normal oper of the main processor
method degrad throughput
laser evapor
ion
intern bond pad select
fusibl link
extern program pin

except in a microprocessor
the special stage
the occurr of an except at ani stage
microprocessor with pipelin system
expans of the number of stage

except in a processor system
reissue the instruct
procedur for the single instruct
instruct processor precis except

execut memori interleav
trail
the number of branche
the complex of risc architectur
symbol program
risc iii
partial unif
mani short branche by condit execut of the variou instruct
iii microprocessor

execut system for instruct
the type code
the long instruct word
plural of the instruct word
plural of instruct
plural instruct code
length from a type code

fast determin
point sticki bit from input operand

first/second hit/mishit
single chip pipelin processor
instruction/data cach in respons

float point multipli
use in digit circuitri
the newton method of reciproc squar root comput of a valu
the machin method of the present embodi
sever comput step
point multipli unit
point adder subtractor unit
newton iter for reciproc squar root
machin method
iter numer techniqu

frequent time
the microprocesor

gate delay
the fact
the clock period of the circuit
retim the circuit
regist in the circuit
regist from a technologi librari

gener regist with subdivis
uo instruct
subdivis type
instruct by regist number

high perform vlsi data filter
vlsi data filter
the data filter
simple numer oper
input data stream

hook
variou featur
test hook function

hybrid
vector imag processor
vector imag
the exemplari processor

inconsist time delay in signal
time delay
signal of multi dimension reconvigur array processor
n dimension array of signal processor

increment acceler
multipl scanlin

individu instruct
the switch
the pipelin identif tag
the appropri instruct
instruct cach associ crossbar switch system

instruct access time
instruct bit a fifo

instruct from instruct cach
verif of real page number of stack
the real page number

instruct in a re order buffer
method for perform

instruct in success
the interfac portion of a coprocessor
pipelin control of the instruct

instruct issue stage stall through use
such inform at a point
respect pipelin

interfac between a processor
the instruct in the block
the cach with an instruct block from main memori
interfac with instruct

interg operand
point unit data path align

linear systol array
valu of the element of a triangular matrix

load oper in a comput system
no condit

locat of a continu group of pixel locat
the z buffer i
single port
segment on a scan line

low power applic
low power parallel analog to digit convert

lower latenc time
the target address of the branch instruct
the regist file in advanc of the branch instruct
the outcom of the branch instruct

macroninstruct
return data in multiprocessor system
queue for invalid

mesh buffer for decompress
three dimension graphic data

method for single operand regist array for vector
the vector oper operand
the use of a single operand regist file
the scalar oper operand
the prior oper
the next sequenti operand address
the next sequenti operand
the instruct repertoir
scalar data

motion vector calcul method
sequenti minimum distort calcul at differ densiti

multi instruct regist mapper
the issuanc of the set of instruct from the processor

multipl instruct launch
unit architectur with symmetr instruct

normal shift predict
operand substract

operand data from the main memori
the instruct control unit

optim dataflow
queue buffer in the data path

other function unit
virtual memori manag the apparatu
the system architectur requir
the softwar base system
the expens
softwar base system
processor with multipl function unit with separ address translat
processor with multipl function unit
pertin inform

parallel access
undue delay
the mmu by an instruct cach
request from sourc of lower prioriti
request from sourc of differ prioriti for immedi process by the mmu

perform control mechan
w clock
the ratio w/r
the level of perform of the processor
r clock

process for freez protect
the mehra process
purif of natur ga liquid product stream

processor system with writeback cach
writeback transact

rapid pipelin recoveri in a microprocessor
sourc operand dependend analys

return address from a return stack storag
the return address these tag

segment of an instruct
such examin
step for the instruct
segment of the instruct

setting
variou type of control circuit
variou type of comput circuit
the control section
the control of a control section
that configur
single chip self configur parallel processor

specul execut of instruct with multipl predict branch
trap condit

stackpoint in a next pipelin stage
the renew

store oper in a comput system
the store oper
the execut of the store oper
the data for the store oper

t coordin
use in a textur
the primit data
the plane equat
the perspect correct factor w at the gradient
the paramet valu of the next pixel in the x direct
the paramet valu for each pixel
the maximum differ a the gradient
the gradient
the edg stepper
the differ between the paramet valu for the current pixel
the adjac pixel in the y direct

the 
the processor at each level

the instruct for execut in respons
valid of the sourc inform
the sourc inform valid

the op cpu
time critic core prioriti scheme

